ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 109

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 108. Peripheral Controller command and register overview
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[2]
[3]
[4]
[5]
[6]
ISP1362_5
Product data sheet
Name
General commands
Read control OUT error code
Read control IN error code
Read endpoint n error code (n = 1 to
14)
Unlock device
Write or read DcScratch register
Read frame number
Read chip ID
Read DcInterrupt register
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) divided by 2.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
During the isochronous transfer in 16-bit mode, because N
Validating an OUT endpoint buffer causes unpredictable behavior of the Peripheral Controller.
Clearing an IN endpoint buffer causes unpredictable behavior of the Peripheral Controller.
Reads a copy of the Status register, executing this command does not clear any status bits or interrupt bits.
15.1.1 DcEndpointConfiguration register (R/W: 30h to 3Fh/20h to 2Fh)
15.1 Initialization commands
Initialization commands are used during the enumeration process of the USB network.
These commands are used to configure and enable embedded endpoints. They also
serve to set the USB assigned address of the Peripheral Controller and to perform a
device reset.
This command is used to access the DcEndpointConfiguration register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), buffer memory size and buffering scheme. It also enables the endpoint buffer
memory. The register bit allocation is shown in
endpoints.
The allocation of the buffer memory takes place only after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although control endpoints
have fixed configurations, they must be included in the initialization sequence and must be
configured with their default values (see
starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration that affects the allocated
memory (size, enable/disable), the buffer memory contents of all endpoints becomes
invalid. Therefore, all valid data must be removed from enabled endpoints before changing
the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoints 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte (code or data)
Destination
DcErrorCode register endpoint 0
OUT
DcErrorCode register endpoint 0
IN
DcErrorCode register endpoint 1
to 14
all registers with write access
DcScratch register
DcFrameNumber register
DcChipID register
DcInterrupt register
Rev. 05 — 8 May 2007
1023, firmware must manage the upper byte.
Table
…continued
Code (Hex)
A0
A1
A2 to AF
B0
B2/B3
B4
B5
C0
14). Automatic buffer memory allocation
Table
109. A bus reset will disable all
Single-chip USB OTG Controller
Transaction
read 1 byte
read 1 byte
read 1 byte
write 2 bytes
write or read 2 bytes
read 1 byte or 2 bytes
read 2 bytes
read 4 bytes
© NXP B.V. 2007. All rights reserved.
ISP1362
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