ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 92

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 68.
ISP1362_5
Product data sheet
Bit
15 to 0
HcTransferCounter register: bit description
Symbol
CounterValue[15:0] R/W
14.4.3 HcTransferCounter register (R/W: 22h/A2h)
14.4.4 Hc PInterrupt register (R/W: 24h/A4h)
Table 66.
Table 67.
Regardless of PIO or DMA data transfer modes, this register is used to initialize the
number of bytes to be transferred to or from the ISTL, INTL or ATL buffer RAM. For the
count value loaded in the register to take effect, the HCD is required to set bit 7 of the
HcDMAConfiguration register to logic 1. When the count value has reached, the Host
Controller must generate an internal EOT signal to set bit 2 of the Hc PInterrupt register,
AllEOTInterrupt, and update the HcBufferStatus register. The bit allocation of the
HcTransferCounter register is given in
Code (Hex): 22 — read
Code (Hex): A2 — write
All the bits in this register are active at power-on reset. None of the active bits, however,
will cause an interrupt on the interrupt pin (INT1), unless they are set by the respective
bits in the Hc PInterruptEnable register and bit 0 of the HcHardwareConfiguration register
is also set.
The bits in this register are cleared only when you write to this register, indicating the bits
to be cleared. To clear all the enabled bits in this register, the HCD must write FFh to this
register.
The bit allocation of the Hc PInterrupt register is given in
Code (Hex): 24 — read
Code (Hex): A4 — write
Bit
4
3 to 1
0
Bit 3
0
0
0
0
1
Access Value
Symbol
DMAEnable
Buffer_Type_Select[2:0] See
DMAReadWriteSelect
HcDMAConfiguration register: bit description
Buffer_Type_Select[2:0]: bit description
Bit 2
0
0
1
1
X
0000h
Bit 1
0
1
0
1
X
Rev. 05 — 8 May 2007
Description
Number of data bytes to be read from or written to the buffer RAM.
Description
0 — DMA is disabled
1 — DMA is enabled
This bit needs to be reset when the DMA transfer is completed.
0 — read from the buffer memory of the Host Controller
1 — write to the buffer memory of the Host Controller
Buffer Type
ISTL0 (default)
ISTL1
INTL
ATL
direct addressing
Table
Table
67.
68.
Single-chip USB OTG Controller
…continued
Table
69.
© NXP B.V. 2007. All rights reserved.
ISP1362
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