ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 58

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
12.4.3.1 Bulk endpoints
12.4.3 End-Of-Transfer conditions
12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the
For a typical bulk transfer, the preceding process is repeated 32 times, once for each
word. After each word, the DcAddress register in the DMA controller is incremented by
two and the byte counter is decremented by two. When using the 16-bit DMA, the number
of transfers is 32, and address incrementing and byte counter decrementing is done by
two for each word.
A DMA transfer to or from a bulk endpoint can be terminated by any of the following
conditions (bit names refer to the DcDMAConfiguration register, see
Table
DcDMACounter register — An EOT from the DcDMACounter register is enabled by
setting bit CNTREN of the DcDMAConfiguration register. The Peripheral Controller has a
16-bit DcDMACounter register, which specifies the number of bytes to be transferred.
When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value
from the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA operation
stops.
Short packet — Normally, the transfer byte count must be set using a control endpoint
before any DMA transfer takes place. When a short packet has been enabled as EOT
indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet
in data. This mechanism permits the use of a fully autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token will
stop the DMA operation after transferring the data bytes of this packet.
Table 19.
[1]
EOT condition
DcDMACounter register
Short packet
DMAEN bit of the
DcDMAConfiguration register
•
•
•
bus control lines (MEMR, MEMW, IOR and IOW) and address lines, the CPU
resumes the execution of instructions.
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1).
A short packet is received on an enabled OUT endpoint (SHORTP = 1).
DMA operation is disabled by clearing the DMAEN bit.
The DMA transfer stops. No interrupt, however, is generated.
120):
Summary of EOT conditions for a bulk endpoint
Rev. 05 — 8 May 2007
OUT endpoint
transfer completes as
programmed in the
DcDMACounter register
short packet is received and
transferred
DMAEN = 0
[1]
Single-chip USB OTG Controller
IN endpoint
transfer completes as
programmed in the
DcDMACounter register
counter reaches zero in the
middle of the buffer
DMAEN = 0
Table 119
[1]
© NXP B.V. 2007. All rights reserved.
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