ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 118

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh)
15.2.4 Validate endpoint buffer (61h to 6Fh)
15.2.5 Clear endpoint buffer (70h, 72h to 7Fh)
Table 126. DcEndpointStatus register: bit description
These commands are used to stall or unstall an endpoint. The commands modify the
content of the DcEndpointStatus register (see
A stalled control endpoint is automatically unstalled when it receives a set-up token,
regardless of the packet content. If the endpoint must stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by using the Unstall Endpoint command or by
receiving a set-up token), it is also re-initialized. This flushes the buffer: if it is an OUT
buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoints 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoints 1 to 14)
Transaction — none (code only)
This command signals the presence of valid data for transmission to the USB host. The
validation occurs by setting the Buffer Full flag of the selected IN endpoint. This indicates
that the data in the buffer is valid and can be sent to the host, when the next IN token is
received. For a double-buffered endpoint, this command switches the current buffer
memory for CPU access.
Remark: For special aspects of the control IN endpoint, see
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoints 1 to 14)
Transaction — none (code only)
This command unlocks and clears the buffer of the selected OUT endpoint, allowing the
reception of new packets. Reception of a complete packet causes the Buffer Full flag of an
OUT endpoint to be set. Any subsequent packets are refused by returning a NAK
condition, until the buffer is unlocked using this command. For a double-buffered endpoint,
this command switches the current buffer memory for CPU access.
Remark: For special aspects of the control OUT endpoint, see
Bit
3
2
1
0
Symbol
OVERWRITE
SETUPT
CPUBUF
-
Description
This bit is set by hardware. Logic 1 indicates that a new set-up packet has
overwritten the previous set-up information, before it was acknowledged
or before the endpoint was stalled. Once writing of the set-up data is
completed, a read back of this register clears this bit.
Firmware must check this bit before sending an acknowledge set-up
command or stalling the endpoint. On reading logic 1, firmware must stop
ongoing set-up actions and wait for a new set-up packet.
Logic 1 indicates that the buffer contains a set-up packet.
This bit indicates which buffer is currently selected for the CPU access
(0 = primary buffer; 1 = secondary buffer).
reserved
Rev. 05 — 8 May 2007
Table
…continued
125).
Single-chip USB OTG Controller
Section
Section
12.3.6.
© NXP B.V. 2007. All rights reserved.
12.3.6.
ISP1362
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