ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 115

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
Table 121. DcDMACounter register: bit allocation
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15.1.7 DcDMACounter register (R/W: F3h/F2h)
15.1.8 Reset device (F6h)
R/W
R/W
15
0
7
0
Table 120. DcDMAConfiguration register: bit description
This command accesses the DcDMACounter register, which consists of two bytes. The bit
allocation is given in
transfer. Reading the register returns the number of remaining bytes in the current
transfer. A bus reset will not change programmed bit values.
The internal DMA counter is automatically reloaded from the DcDMACounter register. For
details, see
Code (Hex): F2/F3 — write or read DcDMACounter register
Transaction — write or read 2 bytes (code or data)
Table 122. DcDMACounter register: bit description
This command resets the Peripheral Controller in the same way as an external hardware
reset by using input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none (code only)
Bit
3
2
1 to 0
Bit
15 to 0
R/W
R/W
14
0
6
0
Symbol
DMAEN
-
BURSTL[1:0] Selects the DMA burst length:
Section
Symbol
DMACR[15:0]
R/W
R/W
13
0
5
0
15.1.6.
Table
Description
Writing logic 1 enables DMA transfer, logic 0 forces the end of an ongoing
DMA transfer. Reading this bit indicates whether DMA is enabled or not
(0 = DMA stopped; 1 = DMA enabled). This bit is cleared by a bus reset.
reserved
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes)
Bus reset value: unchanged.
Rev. 05 — 8 May 2007
121. Writing to the register sets the number of bytes for a DMA
Description
This field indicates the number of bytes for a DMA transfer.
R/W
R/W
12
0
4
0
DMACR[15:8]
DMACR[7:0]
R/W
R/W
11
0
3
0
Single-chip USB OTG Controller
…continued
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
114 of 152
R/W
R/W
8
0
0
0