ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 86

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
15
7
-
-
-
-
-
-
Table 62.
Bit
31 to 21
20
19
18
17
reserved
reserved
22
14
6
-
-
-
-
-
-
HcRhPortStatus[1:2] register: bit description
Symbol
-
PRSC
OCIC
PSSC
PESC
21
13
5
-
-
-
-
-
-
reserved
Rev. 05 — 8 May 2007
Description
reserved
PortResetStatusChange: This bit is set at the end of the 10 ms port
reset signal. The HCD writes logic 1 to clear this bit. Writing logic 0
has no effect.
0 — port reset is not complete
1 — port reset is complete
PortOverCurrentIndicatorChange: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the
root hub changes the PortOverCurrentIndicator (POCI) bit. The HCD
writes logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no change in PortOverCurrentIndicator (POCI)
1 — PortOverCurrentIndicator (POCI) has changed
PortSuspendStatusChange: This bit is set when the full resume
sequence is complete. This sequence includes the 20 ms resume
pulse, LS EOP and 3 ms re-synchronization delay. The HCD writes
logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also
cleared when PortResetStatusChange is set.
0 — resume is not completed
1 — resume is completed
PortEnableStatusChange: This bit is set when hardware events
cause the PortEnableStatus (PES) bit to be cleared. Changes from the
HCD writes do not set this bit. The HCD writes logic 1 to clear this bit.
Writing logic 0 has no effect.
0 — no change in PortEnableStatus (PES)
1 — change in PortEnableStatus (PES)
PRSC
PRS
R/W
R/W
20
12
0
4
0
-
-
OCIC
POCI
R/W
R/W
19
11
0
3
0
-
-
Single-chip USB OTG Controller
PSSC
PSS
R/W
R/W
18
10
0
2
0
-
-
PESC
LSDA
R/W
R/W
PES
R/W
17
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1362
CSC
CCS
PPS
R/W
R/W
R/W
85 of 152
16
0
8
0
0
0