ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 47

• Manufacturer Part Number: ISP1362EE
• Description: IC USB CTRL SNGL CHIP 64TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1362EE

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

NXP Semiconductors
ISP1362_5
Product data sheet
11.8.1 Using internal overcurrent detection circuit
11.6 Features of the interrupt transfer
11.7 Features of the Isochronous (ISO) transfer
11.8 Overcurrent protection circuit
Table 13.
The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable this
feature by setting or resetting AnalogOCEnable (bit 10) of the HcHardwareConfiguration
register. If this feature is disabled, it is assumed that there is an external overcurrent
protection circuitry.
An application using the internal overcurrent detection circuit and internal 15 k pull-down
resistors is shown in
DPn denotes either OTG_DP1 or H_DP2. In this example, the HCD must set both
AnalogOCEnable and ConnectPullDown_DS1 (bit 10 and bit 12 of the
HcHardwareConfiguration register, respectively) to logic 1.
When H_OCn detects an overcurrent status on a downstream port, H_PSWn will output
HIGH to turn off the 5 V power supply to downstream port V
detection, H_PSWn will output LOW to turn on the 5 V power supply to downstream port
V
N bits [7:5]
0
1
2
3
4
5
6
7
•
•
•
•
•
•
•
BUS
An interrupt transaction is periodically sent out, according to the ‘interrupt polling rate’
as defined in the PTD.
An interrupt transaction causes an interrupt to the CPU only if the transaction is
ACK-ed or has error conditions, such as STALL or no respond. An ACK condition
occurs if data is received on the IN token or data is sent out on the OUT token.
An interrupt is activated only once every ms as long as there is ACK for different
interrupt transactions in the interrupt transfer buffer.
Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or send
data for more than 1 ms. This can be done using the parameters in the PTD.
Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.
The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU
the flexibility to decide how much time it takes to read and fill in the ISO data.
The ISTL buffer can be updated on-the-fly by using the direct addressing memory
architecture.
.
Interrupt polling
StartingFrame N[4:0]
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
frame 0 to 31
Figure
Rev. 05 — 8 May 2007
23, where DMn denotes either OTG_DM1 or H_DM2, while
Interrupt polling interval (2
1
2
4
8
16
32
64
128
Single-chip USB OTG Controller
BUS
. When there is no such
© NXP B.V. 2007. All rights reserved.
ISP1362
N
) in ms
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