ISP1362EE ST-Ericsson Inc, ISP1362EE Datasheet - Page 145

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ISP1362EE

Manufacturer Part Number
ISP1362EE
Description
IC USB CTRL SNGL CHIP 64TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362EE

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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NXP Semiconductors
24. Revision history
Table 163. Revision history
ISP1362_5
Product data sheet
Document ID
ISP1362_5
Modifications:
Release date
20070508
The format of this data sheet has been redesigned to comply with the new presentation and
information standard of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Section 2
Table 2 “Pin
Table 29 “OtgInterruptEnable register: bit
Section 14 “Host Controller
Table 36 “HcRevision register: bit
Table 38 “HcControl register: bit
Section 14.1.4 “HcInterruptStatus register (R/W:
Table 42 “HcInterruptStatus register: bit
Table 46 “HcInterruptDisable register: bit
Table 52 “HcFmNumber register: bit
Section 14.2.4 “HcLSThreshold register (R/W:
Table 54 “HcLSThreshold register: bit
Section 14.3 “HC root hub
Table 56 “HcRhDescriptorA register: bit
Section 14.3.2 “HcRhDescriptorB register (R/W:
Section 14.3.4 “HcRhPortStatus[1:2] register (R/W [1]: 15h/95h; [2]:
paragraph.
Table 64 “HcHardwareConfiguration register: bit
5.
Section 14.4.4 “HcmPInterrupt register (R/W:
Table 75 “HcSoftwareReset register: bit
Section 14.9.8 “HcATLPTDDoneThresholdCount register (R/W:
paragraph.
Table 105 “HcATLPTDDoneThresholdCount register: bit
4 to 0.
Section 14.9.9 “HcATLPTDDoneThresholdTimeOut register (R/W:
paragraph.
Table 110 “DcEndpointConfiguration register: bit
Table 114 “DcMode register: bit
Section 15.1.5 “DcInterruptEnable register (R/W:
Table 118 “DcInterruptEnable register: bit
Section 15.1.7 “DcDMACounter register (R/W:
Table 122 “DcDMACounter register: bit
Table 126 “DcEndpointStatus register: bit
Table 128 “DcEndpointStatusImage register: bit
Table 144 “Recommended operating
Section 19.1 “Programmed I/O timing”
Table 152 “Dynamic characteristics: Host Controller programmed interface
description for t
“Features”: updated.
description”: removed table note “All I/O pads are 5 V tolerant”.
AH
.
Data sheet status
Product data sheet
registers”: updated the last paragraph.
Rev. 05 — 8 May 2007
registers”: updated the first paragraph.
description”: updated description for bit 2.
description”: updated description for bits 7 to 6.
description”: updated description for bits 7 to 0.
description”: updated description for bits 15 to 0.
conditions”: added V
description”: updated description for bits 10 to 0.
and
description”: added description for bits 15 to 0.
description”: updated description for bits 1 to 0.
description”: updated the description column.
description”: updated description for bits 6 and 0.
description”: updated description for bit 31.
description”: updated description for all the bits.
description”: updated description for bit 3.
description”: updated the description column.
Section 19.2 “DMA
24h/A4h)”: removed the second paragraph.
11h/91h)”: updated the first paragraph.
F3h/F2h)”: updated the second paragraph.
description”: updated description for bit 3.
description”: updated description for bits 8, 6 and
13h/93h)”: updated the first paragraph.
03h/83h)”: updated the first paragraph.
description”: updated description for bits 7 and 5.
C3h/C2h)”: updated the first paragraph.
Change notice
-
description”: updated description for bits
I(clk)
Single-chip USB OTG Controller
and removed 1.8 V tolerant under V
timing”: added conditions to tables.
51h/D1h)”: updated the first
52h/D2h)”: updated the first
16h/96h)”: updated the first
Supersedes
ISP1362-04
timing”: updated
© NXP B.V. 2007. All rights reserved.
ISP1362
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I
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