PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet
PIC18F8722-I/PT
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PIC18F8722-I/PT Summary of contents
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... Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology 2004 Microchip Technology Inc. PIC18F8722 Family Data Sheet 64/80-Pin, 1-Mbit, Preliminary DS39646B ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ 2004 Microchip Technology Inc. ...
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... PIC18F8722 128K 65536 3936 2004 Microchip Technology Inc. PIC18F8722 FAMILY Power-Managed Modes: • Run: CPU on, peripherals on • Idle: CPU off, peripherals on • Sleep: CPU off, peripherals off • Idle mode currents down to 15 µA typical • Sleep current down to 0.2 µA typical • ...
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... PIC18F8722 FAMILY Pin Diagrams 64-Pin TQFP RE1/WR/P2C 1 RE0/RD/P2D 2 RG0/ECCP3/P3A 3 RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3/CCP4/P3D 6 RG5/MCLR RG4/CCP5/P1D RF7/SS1 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX configuration bit. DS39646B-page PIC18F6527 42 PIC18F6622 41 PIC18F6627 40 PIC18F6722 Preliminary RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 ...
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... RF3/AN8 17 RF2/AN7/C1OUT 18 (2) RH7/AN15/P1B 19 (2) RH6/AN14/P1C Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F8722 FAMILY PIC18F8527 52 PIC18F8622 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 429 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 429 Index .................................................................................................................................................................................................. 431 On-Line Support................................................................................................................................................................................. 443 Systems Information and Upgrade Hot Line ...................................................................................................................................... 443 Reader Response .............................................................................................................................................................................. 444 PIC18F8722 Family Product Identification System............................................................................................................................ 445 DS39646B-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Preliminary DS39646B-page 5 ...
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... PIC18F8722 FAMILY NOTES: DS39646B-page 6 Preliminary 2004 Microchip Technology Inc. ...
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... MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F8722 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators • ...
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... Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18F8722 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instruc- tions and an Indexed Addressing mode. This ...
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... Details on Individual Family Members Devices in the PIC18F8722 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (48 PIC18F6527/8527 devices, 64 Kbytes for ...
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... PIC18F8722 FAMILY TABLE 1-2: DEVICE FEATURES (PIC18F8527/8622/8627/8722) Features PIC18F8527 Operating Frequency DC – 40 MHz Program Memory (Bytes) 48K Program Memory (Instructions) 24576 Data Memory (Bytes) 3936 Data EEPROM Memory (Bytes) 1024 Interrupt Sources I/O Ports Ports Timers Capture/Compare/PWM Modules Enhanced Capture/Compare/ PWM Modules ...
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... RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Data Bus<8> Data Latch 8 8 Data Memory (3 ...
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... PIC18F8722 FAMILY FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (48/64/96/128 Kbytes) Data Latch Instruction Bus <16> AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE and PORTH) State Machine Control Signals (3) Internal OSC1 Oscillator ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type Master Clear (input) or programming voltage (input Digital input Master Clear (Reset) input ...
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... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/HLVDIN 27 RA5 AN4 HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ...
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... Power Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 29 RC1 T1OSI (1) ECCP2 (1) P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK1/SCL1 34 RC3 SCK1 SCL1 RC4/SDI1/SDA1 35 RC4 SDI1 SDA1 RC5/SDO1 36 RC5 SDO1 RC6/TX1/CK1 31 RC6 TX1 ...
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... I = Input P = Power Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O. I/O TTL Parallel Slave Port data ...
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... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/RD/P2D 2 RE0 RD P2D RE1/WR/P2C 1 RE1 WR P2C RE2/CS/P2B 64 RE2 CS P2B RE3/P3C 63 RE3 P3C RE4/P3B 62 RE4 P3B RE5/P1C 61 RE5 P1C RE6/P1B 60 RE6 P1B RE7/ECCP2/P2A 59 RE7 (2) ECCP2 (2) P2A Legend: TTL = TTL compatible input ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O. I Analog Analog input 5 ...
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... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 3 RG0 ECCP3 P3A RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3/CCP4/P3D 6 RG3 CCP4 P3D RG4/CCP5/P1D 8 RG4 CCP5 P1D RG5 V 9, 25, 41 10, 26, 38 Legend: TTL = TTL compatible input ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type Master Clear (input) or programming voltage (input Digital input ...
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... PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RA0/AN0 30 RA0 AN0 RA1/AN1 29 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 34 RA4 T0CKI RA5/AN4/HLVDIN 33 RA5 AN4 HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ...
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... Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 36 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 35 RC1 T1OSI (2) ECCP2 (2) P2A RC2/ECCP1/P1A 43 RC2 ECCP1 P1A RC3/SCK1/SCL1 44 RC3 SCK1 SCL1 RC4/SDI1/SDA1 45 RC4 SDI1 SDA1 RC5/SDO1 46 RC5 SDO1 RC6/TX1/CK1 37 RC6 TX1 ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/AD8/RD/P2D 4 RE0 AD8 RD P2D RE1/AD9/WR/P2C 3 RE1 AD9 WR P2C RE2/AD10/CS/P2B 78 RE2 AD10 CS P2B RE3/AD11/P3C 77 RE3 AD11 (4) P3C RE4/AD12/P3B 76 RE4 AD12 (4) P3B RE5/AD13/P1C 75 RE5 AD13 (4) P1C RE6/AD14/P1B 74 RE6 AD14 ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 5 RG0 ECCP3 P3A RG1/TX2/CK2 6 RG1 TX2 CK2 RG2/RX2/DT2 7 RG2 RX2 DT2 RG3/CCP4/P3D 8 RG3 CCP4 P3D RG4/CCP5/P1D 10 RG4 CCP5 P1D RG5 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RJ0/ALE 62 RJ0 ALE RJ1/OE 61 RJ1 OE RJ2/WRL 60 RJ2 WRL RJ3/WRH 59 RJ3 WRH RJ4/BA0 39 RJ4 BA0 RJ5/CE 40 RJ4 CE RJ6/LB 41 RJ6 LB RJ7/UB 42 RJ7 UB V 11, 31, 51 12, 32, 48 Legend: TTL = TTL compatible input ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F8722 family of devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL High-Speed Crystal/Resonator with PLL enabled 5 ...
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... PIC18F8722 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR QUARTZ CRYSTALS Typical Capacitor Values Crystal Tested: Osc Type Freq kHz MHz MHz MHz MHz MHz MHz 22 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test ...
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... EXT 20 pF ≤ C ≤ 300 pF EXT 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... PIC18F8722 FAMILY 2.6 Internal Oscillator Block The PIC18F8722 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. ...
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... Minimum frequency Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift affect the controller operation in a variety of ways possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...
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... PIC18F8722 FAMILY 2.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F8722 family of devices are shown in Figure 2-11. See Section 25.0 “Special Features of the CPU” for Configuration register details. ...
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... Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS The PIC18F8722 family of devices contains circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... Modifying the SCSI:SCSO bits will cause an immediate clock source switch. 5: Modifying the IRCF3:IRCF0 bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY (1) R/W-0 R/W-0 R R-0 IRCF1 ...
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... PIC18F8722 FAMILY 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the configured oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in crystal oscillator modes) will stop oscillating. ...
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... POWER-MANAGED MODES The PIC18F8722 family of devices offers a total of seven operating modes for more efficient power man- agement. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: • ...
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... PIC18F8722 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • ...
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... RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2004 Microchip Technology Inc. PIC18F8722 FAMILY n-1 n (1) ...
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... PIC18F8722 FAMILY If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, ...
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... Sleep Mode The power-managed Sleep mode in the PIC18F8722 family of devices is identical to the legacy Sleep mode offered in all other PICmicro devices entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared ...
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... PIC18F8722 FAMILY 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2004 Microchip Technology Inc. PIC18F8722 FAMILY On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execu- tion continues or resumes without branching (see Section 10.0 “ ...
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... PIC18F8722 FAMILY 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT HSPLL modes ...
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... RESET The PIC18F8722 family of devices differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F8722 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 IPEN SBOREN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit If BOREN1:BOREN0 = 01 BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00 11: Bit is disabled and read as ‘ ...
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... The MCLR pin is not driven low by any internal Resets, including the WDT. In the PIC18F8722 family of devices, the MCLR input can be disabled with the MCLRE configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.5 “PORTE, TRISE and LATE Registers” ...
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... PIC18F8722 FAMILY 4.4 Brown-out Reset (BOR) The PIC18F8722 family of devices implements a BOR circuit that provides the user with a number of con- figuration and power-saving options. The BOR is con- trolled by the BORV1:BORV0 and BOREN1:BOREN0 configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. ...
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... Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bring- ing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18F8722 family device operating in parallel. (2) Power-up ...
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... PIC18F8722 FAMILY FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... V DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ the nominal time required for the PLL to lock. T PLL 2004 Microchip Technology Inc. PIC18F8722 FAMILY , V RISE > PWRT T PWRT T OST T PWRT T OST T PLL ...
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... PIC18F8722 FAMILY 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices FSR1H 6X27 6X22 8X27 FSR1L 6X27 6X22 8X27 BSR 6X27 6X22 8X27 INDF2 6X27 6X22 8X27 POSTINC2 6X27 6X22 8X27 POSTDEC2 6X27 6X22 8X27 PREINC2 6X27 6X22 8X27 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR3 6X27 6X22 8X27 PIR3 6X27 6X22 8X27 PIE3 6X27 6X22 8X27 IPR2 6X27 6X22 8X27 PIR2 6X27 6X22 8X27 PIE2 6X27 6X22 8X27 IPR1 6X27 6X22 8X27 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, WDT Reset, Brown-out Reset ...
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... PIC18F8722 FAMILY NOTES: DS39646B-page 62 Preliminary 2004 Microchip Technology Inc. ...
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... Flash memory. Attempts to read above the physical limit of the on-chip Flash (0BFFFh for the PIC18F8527, 0FFFFh for the PIC18F8622, 17FFFh for the PIC18F8627, 1FFFFh for the PIC18F8722) causes a read of all ‘0’s (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6527/6622/6627/6722 devices. • ...
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... PIC18F8722 FAMILY FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F8722 FAMILY DEVICES CALL,RCALL,RETURN RETFIE,RETLW On-Chip On-Chip Program Memory Program Memory PIC18FX527 PIC18FX622 0BFFFh 0C000h Read ‘0’ Read ‘0’ TABLE 5-1: MEMORY ACCESS FOR PIC18F8527/8622/8627/8722 PROGRAM MEMORY MODES Internal Program Memory ...
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... FIGURE 5-2: MEMORY MAPS FOR PIC18F8722 FAMILY PROGRAM MEMORY MODES Microprocessor Mode 000000h 000000h On-Chip Program Memory 0007FFh (No 000FFFh access) 001FFFh 000800h 001000h External 002000h Program Memory 1FFFFFh 1FFFFFh External On-Chip Memory Flash Note 1: PIC18F6527 and PIC18F8527. 2: PIC18F6622 and PIC18F8622. 3: PIC18F6627 and PIC18F8627. ...
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... PIC18F8722 FAMILY 5.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC< ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY When the stack has been popped enough times to unload the stack, the next POP will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs ...
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... PIC18F8722 FAMILY 5.1.3.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F8722 FAMILY on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4 ...
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... PIC18F8722 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘ ...
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... ADDWF 2004 Microchip Technology Inc. PIC18F8722 FAMILY the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a condi- tional instruction that changes the PC ...
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... RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; the PIC18F8722 family of devices implements all 16 banks. Figure 5-6 shows the data memory organization for the PIC18F8722 family of devices ...
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... FIGURE 5-6: DATA MEMORY MAP FOR THE PIC18F8722 FAMILY OF DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 ...
Page 76
... PIC18F8722 FAMILY FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 77
... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 5-2 and Table 5-3. TABLE 5-2: SPECIAL FUNCTION REGISTER MAP FOR THE PIC18F8722 FAMILY OF DEVICES Address Name Address FFFh ...
Page 78
... PIC18F8722 FAMILY TABLE 5-3: REGISTER FILE SUMMARY File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) (6) (6) STKPTR STKFUL STKUNF PCLATU — — PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
Page 79
... RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as 6: Bit 7 and Bit 6 are cleared by user software POR. 7: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 4 Bit 3 Bit 2 — N ...
Page 80
... PIC18F8722 FAMILY TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 PSPCON IBF OBF IBOV SPBRG1 EUSART1 Baud Rate Generator Register Low Byte RCREG1 EUSART1 Receive Register TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN EEADRH — ...
Page 81
... RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as 6: Bit 7 and Bit 6 are cleared by user software POR. 7: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 4 Bit 3 Bit 2 RJ5 RJ4 ...
Page 82
... PIC18F8722 FAMILY 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC bits, the results of the instruction are not written ...
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... Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘ ...
Page 84
... PIC18F8722 FAMILY 5.4.3.1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion ...
Page 85
... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM ...
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... PIC18F8722 FAMILY FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When ‘a’ and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is inter- preted as a location in the Access RAM between 060h and 0FFh ...
Page 87
... F80h by using the BSR. FFFh 2004 Microchip Technology Inc. PIC18F8722 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. ...
Page 88
... PIC18F8722 FAMILY NOTES: DS39646B-page 86 Preliminary 2004 Microchip Technology Inc. ...
Page 89
... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 90
... PIC18F8722 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 91
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-0 R/W-x R/W-0 — FREE ...
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... PIC18F8722 FAMILY 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER ...
Page 93
... MOVF TABLAT, W MOVF WORD_ODD 2004 Microchip Technology Inc. PIC18F8722 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F8722 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 95
... CFGS bit to access program memory; • set WREN to enable byte writes. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer ...
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... PIC18F8722 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64' MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER BRA ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
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... PIC18F8722 FAMILY NOTES: DS39646B-page 96 Preliminary 2004 Microchip Technology Inc. ...
Page 99
... For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
Page 100
... PIC18F8722 FAMILY 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
Page 101
... Microchip Technology Inc. PIC18F8722 FAMILY 7.2.1 21-BIT ADDRESSING As an extension of 20-bit address width operation, the external memory bus can also fully address a 2 Mbyte memory space. This is done by using the Bus Address bit 0 (BA0) control line as the Least Significant bit of the address ...
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... PIC18F8722 FAMILY 7.4 Program Memory Modes and the External Memory Bus PIC18F8527/8622/8627/8722 devices are capable of operating in any one of four program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depends on the program memory mode selected, as well as the setting of the EBDIS bit ...
Page 103
... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F8722 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. D< ...
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... PIC18F8722 FAMILY 7.5.2 16-BIT WORD WRITE MODE Figure 7-2 shows an example of 16-bit Word Write mode for PIC18F8527/8622/8627/8722 devices. This mode is used for word-wide memories which includes some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
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... Upper-order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 106
... PIC18F8722 FAMILY 7.5.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 through Figure 7-6. All examples assume either 20-bit or 21-bit address widths. FIGURE 7-4: ...
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... ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution Note 1: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h ...
Page 108
... PIC18F8722 FAMILY 7.6 8-bit Data Width Modes In 8-bit Data Width mode, the external memory bus operates only in Multiplexed mode; that is, data shares the 8 least significant bits of the address bus. Figure 7-7 shows an example of 8-bit Multiplexed mode for PIC18F8527/8622/8627/8722 devices. This mode is used for a single 8-bit memory connected for 16-bit operation ...
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... CE ALE OE Opcode Fetch Memory Cycle TBLRD * from 000100h Instruction INST(PC – 2) Execution Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 03Ah CCFh ABh 55h 0Eh 33h ...
Page 110
... PIC18F8722 FAMILY FIGURE 7-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE (1) 00h A<19:16> (1) AD<15:8> 3Ah AD<7:0> AAh 00h 03h BA0 CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. ...
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... This register is not implemented on 64-pin devices. 2: Unimplemented in PIC18F6527/6622/6627/6722 devices. 2004 Microchip Technology Inc. PIC18F8722 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are sus- pended. The state of the external bus is frozen with the ...
Page 112
... PIC18F8722 FAMILY NOTES: DS39646B-page 110 Preliminary 2004 Microchip Technology Inc. ...
Page 113
... EEPROM. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
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... PIC18F8722 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers ...
Page 115
... BSF INTCON, GIE BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F8722 FAMILY Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
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... PIC18F8722 FAMILY 8.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect configuration bit. Refer to Section 25.0 “ ...
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... IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — — — — ...
Page 118
... PIC18F8722 FAMILY NOTES: DS39646B-page 116 Preliminary 2004 Microchip Technology Inc. ...
Page 119
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2004 Microchip Technology Inc. PIC18F8722 FAMILY EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 9-2: ...
Page 120
... PIC18F8722 FAMILY Example 9-3 shows the sequence unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ...
Page 121
... INTERRUPTS The PIC18F8722 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress ...
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... PIC18F8722 FAMILY FIGURE 10-1: PIC18F8722 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 4:0> PIE2<7:6, 4:0> IPR2<7:6, 4:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 4:0> PIE2<7:6, 4:0> IPR2<7:6, 4:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> DS39646B-page 120 ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
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... PIC18F8722 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
Page 125
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 ...
Page 126
... PIC18F8722 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 127
... Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-0 R/W-0 R/W-0 — EEIF BCL1IF HLVDIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 128
... PIC18F8722 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 SSP2IF BCL2IF bit 7 bit 7 SSP2IF: MSSP2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software Waiting to transmit/receive bit 6 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit bus collision has occurred while the MSSP2 module configured in I ...
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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 130
... PIC18F8722 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 OSCFIE CMIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Interrupt Enable bit ...
Page 131
... CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY R-0 R-0 R/W-0 R/W-0 RC2IE TX2IE TMR4IE CCP5IE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 132
... PIC18F8722 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-1 R/W-1 R/W-1 — EEIP BCL1IP HLVDIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 134
... PIC18F8722 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-0 R/W-0 SSP2IP BCL2IP bit 7 bit 7 SSP2IP: MSSP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: MSSP2 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit ...
Page 135
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-1 R-1 R-1 — Writable bit U = Unimplemented bit, read as ‘ ...
Page 136
... PIC18F8722 FAMILY 10.6 INTn Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
Page 137
... Port Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 138
... PIC18F8722 FAMILY TABLE 11-1: PORTA FUNCTIONS TRIS Pin Name Function I/O Setting RA0/AN0 RA0 0 1 AN0 1 RA1/AN1 RA1 0 1 AN1 1 RA2/AN2/V - RA2 REF 0 1 AN2 REF RA3/AN3/V + RA3 0 REF 1 AN3 REF RA4/T0CKI RA4 0 1 T0CKI x RA5/AN4/HLVDIN RA5 0 1 AN4 1 HLVDIN 1 OSC2/CLKO/RA6 ...
Page 139
... The pull-ups are disabled on a Power-on Reset. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison) ...
Page 140
... PIC18F8722 FAMILY TABLE 11-3: PORTB FUNCTIONS TRIS Pin Name Function Setting RB0/INT0/FLT0 RB0 0 1 INT0 1 FLT0 1 RB1/INT1 RB1 0 1 INT1 1 RB2/INT2 RB2 0 1 INT2 1 RB3/INT3/ RB3 0 ECCP2/P2A 1 INT3 1 (1) ECCP2 0 1 (1) 0 P2A RB4/KBI0 RB4 0 1 KBI0 1 RB5/KBI1/PGM RB5 0 1 KBI1 ...
Page 141
... TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 LATB3 ...
Page 142
... PIC18F8722 FAMILY 11.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i ...
Page 143
... C/SMB = I C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when CCP2MX configuration bit is set. 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATC<0> data output. ...
Page 144
... PIC18F8722 FAMILY TABLE 11-5: PORTC FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RC6/TX1/CK1 RC6 0 1 TX1 0 CK1 0 1 RC7/RX1/DT1 RC7 0 1 RX1 1 DT1 1 1 Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output; ...
Page 145
... PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0). The TRISD bits are also overridden. 2004 Microchip Technology Inc. PIC18F8722 FAMILY PORTD can also be configured to function as an 8-bit wide parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, parallel port data takes priority over other digital I/O (but not the external memory interface) ...
Page 146
... PIC18F8722 FAMILY TABLE 11-7: PORTD FUNCTIONS TRIS Pin Name Function Setting RD0/AD0/PSP0 RD0 0 1 (1) AD0 x x PSP0 x x RD1/AD1/PSP1 RD1 0 1 (1) AD1 x x PSP1 x x RD2/AD2/PSP2 RD2 0 1 (1) AD2 x x PSP2 x x RD3/AD3/PSP3 RD3 0 1 (1) AD3 x x PSP3 x x RD4/AD4/ RD4 ...
Page 147
... Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD7 LATD6 TRISD TRISD7 TRISD6 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATD<5> data output PORTD<5> data input. O DIG External memory interface, address/data bit 5 output. Takes priority over PSP, MSSP and port data. ...
Page 148
... PIC18F8722 FAMILY 11.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i ...
Page 149
... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode). 2: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATE< ...
Page 150
... PIC18F8722 FAMILY TABLE 11-9: PORTE FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RE5/AD13/P1C RE5 0 1 (2) AD13 x x P1C 0 RE6/AD14/P1B RE6 0 1 (2) AD14 x x P1B 0 RE7/AD15/ RE7 0 ECCP2/P2A 1 (2) AD15 x x (1) ECCP2 0 1 (1) P2A 0 Legend: PWR = Power Supply Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’ ...
Page 151
... CMCON register. To use RF0:RF6 as digital inputs necessary to turn off the A/D inputs. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Note Power-on Reset, the RF6:RF0 pins are configured as analog inputs and read as ‘0’ configure PORTF as digital I/O, set the ADCON1 register ...
Page 152
... PIC18F8722 FAMILY TABLE 11-11: PORTF FUNCTIONS TRIS Pin Name Function Setting RF0/AN5 RF0 0 1 AN5 1 RF1/AN6/C2OUT RF1 0 1 AN6 1 C2OUT 0 RF2/AN7/C1OUT RF2 0 1 AN7 1 C1OUT 0 RF3/AN8 RF3 0 1 AN8 1 RF4/AN9 RF4 0 1 AN9 1 RF5/AN10/CV RF5 0 REF 1 AN10 REF RF6/AN11 RF6 0 1 AN11 ...
Page 153
... TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The sixth pin of PORTG (RG5/MCLR/V only pin. Its operation is controlled by the MCLRE configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’ ...
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... PIC18F8722 FAMILY TABLE 11-13: PORTG FUNCTIONS TRIS Pin Name Function Setting RG0/ECCP3/P3A RG0 0 1 ECCP3 0 1 P3A 0 RG1/TX2/CK2 RG1 0 1 TX2 0 CK2 0 1 RG2/RX2/DT2 RG2 0 1 RX2 1 DT2 1 1 RG3/CCP4/P3D RG3 0 1 CCP4 0 1 P3D 0 RG4/CCP5/P1D RG4 0 1 CCP5 0 1 P1D ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 and LATG5 are only available when MCLR is disabled (MCLRE configuration bit = 0; otherwise, RG5 and LATG5 read as ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F8722 FAMILY 11.8 PORTH, LATH and TRISH Registers Note: PORTH is available PIC18F8527/8622/8627/8722 devices. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... TRISH6 PORTH RH7 RH6 LATH LATH7 LATH6 ADCON1 — — 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O Type DIG LATH<0> data output PORTH<0> data input. DIG External memory interface, address line 16. Takes priority over port data. DIG LATH<1> data output. ...
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... PIC18F8722 FAMILY 11.9 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available PIC18F8527/8622/8627/8722 devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... Name Bit 7 Bit 6 PORTJ RJ7 RJ6 LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output. Takes priority over digital I/O. ...
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... PIC18F8722 FAMILY 11.10 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set asynchronously readable and writable by the external world through the RD and WR control input pins. Note: For PIC18F8527/8622/8627/8722 devices, the Parallel Slave Port is available only in Microcontroller mode ...
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... PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC18F8722 FAMILY FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 11-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD7 LATD6 ...
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... Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... PIC18F8722 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F8722 FAMILY NOTES: DS39646B-page 164 Preliminary 2004 Microchip Technology Inc. ...
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... Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F8722 FAMILY 13.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM ...
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... T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F8722 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F8722 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
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... PIC18F8722 FAMILY NOTES: DS39646B-page 170 Preliminary 2004 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
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... PIC18F8722 FAMILY 14.2 Timer2 Interrupt Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1) ...
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... PIC18F8722 FAMILY 15.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. ...
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... T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F8722 FAMILY NOTES: DS39646B-page 176 Preliminary 2004 Microchip Technology Inc. ...
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... Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP modules. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... PIC18F8722 FAMILY 16.2 Timer4 Interrupt The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES The PIC18F8722 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) standard Capture and Compare modes, as well as Enhanced PWM modes ...
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... PIC18F8722 FAMILY 17.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... RG3/CCP4 pin and Edge Detect CCP1CON<3:0> Q’s 2004 Microchip Technology Inc. PIC18F8722 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... PIC18F8722 FAMILY 17.3 Compare Mode In Compare mode, the 16-bit value of the CCPRx registers is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remain unchanged (that is, reflects the state of the ...
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... P3M0 CCP4CON — — CCP5CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
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... PIC18F8722 FAMILY 17.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. ...
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... Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 17.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 (PR4) register ...
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... PIC18F8722 FAMILY TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN SBOREN PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR3 SSP2IF BCL2IF PIE3 SSP2IE BCL2IF IPR3 SSP2IP BCL2IP TMR2 Timer2 Register ...
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... ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE In the PIC18F8722 family of devices, ECCP1, ECCP2 and ECCP3 are implemented as a standard CCP module with Enhanced PWM capabilities. These include the provision for output channels, user selectable polarity, dead-band control and automatic shutdown and restart. The enhanced features are discussed in detail in Section 18.4 “ ...
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... PIC18F8722 FAMILY 18.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCPx pin assignments are constant, while others change based on device configuration ...
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... Note 1: With ECCP1 in Quad PWM mode, the CCP5 module’s output overrides P1D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. 2004 Microchip Technology Inc. PIC18F8722 FAMILY RC2 RE6 RE5 PIC18F6527/6622/6627/6722 Devices: RE6 ...
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... PIC18F8722 FAMILY TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 CCP2CON ECCP Mode Configuration PIC18F6527/6622/6627/6722 Devices, CCP2MX = 1: Compatible CCP RB3/INT3 00xx 11xx Dual PWM RB3/INT3 10xx 11xx Quad PWM RB3/INT3 x1xx 11xx PIC18F6527/6622/6627/6722 Devices CCP2MX = 0: Compatible CCP RB3/INT3 00xx 11xx Dual PWM RB3/INT3 ...
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... Note 1: With ECCP3 in Quad PWM mode, the CCP4 module’s output overrides P3D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. 2004 Microchip Technology Inc. PIC18F8722 FAMILY RG0 RE4 RE3 PIC18F6527/6622/6627/6722 Devices: RE4 ...
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... PIC18F8722 FAMILY 18.1.3 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP modules can utilize Timers depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. ...
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... In PWM mode, CCPR1H is a read-only register. TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2004 Microchip Technology Inc. PIC18F8722 FAMILY P1M1<1:0> CCP1M<3:0> ECCP1/P1A P1B Output R Q Controller ...
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... PIC18F8722 FAMILY 18.4.3 PWM OUTPUT CONFIGURATIONS The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: • Single Output • Half-Bridge Output • Full-Bridge Output, Forward mode • Full-Bridge Output, Reverse mode FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL CCP1CON<7:6> ...
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... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable Dead-Band Delay”). 2004 Microchip Technology Inc. PIC18F8722 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay Preliminary ...
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... PIC18F8722 FAMILY 18.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output sig- nal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2004 Microchip Technology Inc. PIC18F8722 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. Alternatively, P1B and P1C can be assigned to PORTH< ...
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... PIC18F8722 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F6X27/6X22/8X27/8X22 P1A P1B P1C P1D 18.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...