PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 314
PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8722-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
70
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
128K Bytes
Ram Size
3.9K Bytes
Speed
40 MHz
Timers
2-8 bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8722-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F8722 FAMILY
25.2
For the PIC18F8722 family of devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 25-1:
DS39646B-page 312
Change on IRCF bits
All Device Resets
INTRC Source
WDTPS<4:1>
Watchdog Timer (WDT)
SWDTEN
CLRWDT
WDTEN
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
÷128
4
Preliminary
Programmable Postscaler
1:1 to 1:32,768
25.2.1
Register 25-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit, but only if the configuration bit has
disabled the WDT.
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
Reset
2004 Microchip Technology Inc.
WDT
Reset
Wake-up from
Power-Managed
Modes
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