PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 149

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 11-9:
 2004 Microchip Technology Inc.
RE0/AD8/
RD/P2D
RE1/AD9/
WR/P2C
RE2/AD10/
CS/P2B
RE3/AD11/P3C
RE4/AD12/P3B
Legend:
Note 1:
Pin Name
2:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).
Implemented on 80-pin devices only.
Function
PORTE FUNCTIONS
AD10
AD12
AD11
AD8
AD9
RE0
P2D
RE1
P2C
RE2
RE3
P3C
RE4
P2B
P3B
WR
RD
CS
(2)
(2)
(2)
(2)
(2)
Setting
TRIS
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
Preliminary
LATE<0> data output.
PORTE<0> data input.
External memory interface, address/data bit 8 output. Takes priority
over ECCP and port data.
External memory interface, data bit 8 input.
Parallel Slave Port read enable control input.
ECCP2 Enhanced PWM output, channel D. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<1> data output.
PORTE<1> data input.
External memory interface, address/data bit 9 output. Takes priority
over ECCP and port data.
External memory interface, data bit 9 input.
Parallel Slave Port write enable control input.
ECCP2 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<2> data output.
PORTE<2> data input.
External memory interface, address/data bit 10 output. Takes priority
over ECCP and port data.
External memory interface, data bit 10 input.
Parallel Slave Port chip select control input.
ECCP2 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<3> data output.
PORTE<3> data input.
External memory interface, address/data bit 11 output. Takes priority
over ECCP and port data.
External memory interface, data bit 11 input.
ECCP3 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<4> data output.
PORTE<4> data input.
External memory interface, address/data bit 12 output. Takes priority
over ECCP and port data.
External memory interface, data bit 12 input.
ECCP3 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
PIC18F8722 FAMILY
Description
DS39646B-page 147