PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 232

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
19.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPxCON1 and by setting
the SSPEN bit. In Master mode, the SCLx and SDAx
lines are manipulated by the MSSP hardware if the
TRIS bits are set.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 19-16:
DS39646B-page 230
SDAx
SCLx
Assert a Start condition on SDAx and SCLx.
Assert a Repeated Start condition on SDAx and
SCLx.
Write to the SSPxBUF register initiating
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDAx and SCLx.
2
C bus may be taken when the P bit is set, or the
MASTER MODE
2
C bus operations based on Start and
2
C port to receive data.
MSSP BLOCK DIAGRAM (I
SDAx In
Bus Collision
SCLx In
Read
MSb
Write Collision Detect
end of XMIT/RCV
Start bit, Stop bit,
State Counter for
Clock Arbitration
Acknowledge
Stop bit Detect
Start bit Detect
SSPxBUF
SSPxSR
Generate
Preliminary
2
C™ MASTER MODE)
LSb
Write
The following events will cause the SSP Interrupt Flag
bit, SSPxIF, to be set (and SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Internal
Note:
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start condi-
tion is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
2
C Master mode, does not allow queueing
 2004 Microchip Technology Inc.
SSPM3:SSPM0
SSPxADD<6:0>
Generator
Baud
Rate