PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 337
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8722-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
70
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
128K Bytes
Ram Size
3.9K Bytes
Speed
40 MHz
Timers
2-8 bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8722-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction:
After Instruction:
Decode
PORTC =
PORTC =
Q1
register ‘f’
BTG
Bit Toggle f
BTG f, b {,a}
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
(f<b>) → f<b>
None
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Read
0111
Q2
0111 0101 [75h]
0110 0101 [65h]
PORTC,
bbba
Process
Data
Q3
4, 0
ffff
register ‘f’
Write
Q4
ffff
BOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
PIC18F8722 FAMILY
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Overflow
If Overflow
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Overflow
BOV
-128 ≤ n ≤ 127
if Overflow bit is ‘1’
(PC) + 2 + 2n → PC
None
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
0100
BOV
operation
Process
Process
Data
Data
No
Q3
Q3
DS39646B-page 335
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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