PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 147

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 11-7:
TABLE 11-8:
 2004 Microchip Technology Inc.
PORTD
LATD
TRISD
RD5/AD5/
PSP5/SDI2
/SDA2
RD6/AD6/
PSP6/SCK2/
SCL2
RD7/AD7/
PSP7/SS2
Legend:
Note 1:
Pin Name
Name
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 80-pin devices only.
TRISD7
LATD7
Bit 7
RD7
Function
PORTD FUNCTIONS (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
AD5
AD6
AD7
PSP5
SDA2
PSP6
SCK2
PSP7
SCL2
SDI2
RD5
RD6
RD7
SS2
(1)
(1)
(1)
TRISD6
LATD6
Bit 6
RD6
Setting
TRIS
0
1
x
x
x
x
1
1
1
0
1
x
x
x
x
0
1
0
1
0
1
x
x
x
x
1
TRISD5
LATD5
Bit 5
RD5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O Type
I
I
2
2
DIG-3
C/SMB I
C/SMB I
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
TTL
TTL
ST
ST
ST
ST
ST
TRISD4
LATD4
Preliminary
Bit 4
RD4
LATD<5> data output.
PORTD<5> data input.
External memory interface, address/data bit 5 output. Takes priority
over PSP, MSSP and port data.
External memory interface, data bit 5 input.
PSP read data output (LATD<5>). Takes priority over port data.
PSP write data input.
SPI™ data input (MSSP2 module).
I
data.
setting.
LATD<6> data output.
PORTD<6> data input.
External memory interface, address/data bit 6 output. Takes priority
over PSP, MSSP and port data.
External memory interface, data bit 6 input.
PSP read data output (LATD<6>). Takes priority over port data.
PSP write data input.
SPI clock output (MSSP2 module). Takes priority over PSP and port
data.
SPI clock input (MSSP2 module).
I
data.
setting.
LATD<7> data output.
PORTD<7> data input.
External memory interface, address/data bit 7 output. Takes priority
over PSP and port data.
External memory interface, data bit 7 input.
PSP read data output (LATD<7>). Takes priority over port data.
PSP write data input.
Slave select input for SSP (MSSP2 module).
2
2
2
2
C™ data output (MSSP2 module). Takes priority over PSP and port
C data input (MSSP2 module); input type depends on module
C clock output (MSSP2 module). Takes priority over PSP and port
C clock input (MSSP2 module); input type depends on module
TRISD3
LATD3
Bit 3
RD3
PIC18F8722 FAMILY
TRISD2
LATD2
Bit 2
RD2
Description
TRISD1
LATD1
Bit 1
RD1
TRISD0
LATD0
Bit 0
RD0
DS39646B-page 145
on page
Values
Reset
60
60
60