PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 198

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
18.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output sig-
nal is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin
(Figure 18-4). This mode can be used for half-bridge
applications, as shown in Figure 18-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
P1DC6:P1DC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 18.4.6
“Programmable Dead-Band Delay” for more details
on dead-band delay operations.
FIGURE 18-5:
DS39646B-page 196
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
PIC18F6X27/6X22/8X27/8X22
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18F6X27/6X22/8X27/8X22
P1A
P1B
P1A
P1B
FET
Driver
FET
Driver
Preliminary
FET
Driver
FET
Driver
The P1A and P1B outputs are multiplexed with the
PORTC<2> and PORTE<6> data latches. Alterna-
tively, P1B can be assigned to PORTH<7> by program-
ming the ECCPMX configuration bit to ‘0’. See
Table 18-1, Table 18-2 and Table 18-3 for more
information. The associated TRIS bit must be cleared
to configure P1A and P1B as outputs.
FIGURE 18-4:
Note 1: At this time, the TMR2 register is equal to the
P1A
P1B
td = Dead Band Delay
(2)
(2)
2: Output signals are shown as active-high.
Load
V+
V-
(1)
PR2 register.
V+
V-
td
Duty Cycle
Period
Load
td
HALF-BRIDGE PWM
OUTPUT
 2004 Microchip Technology Inc.
FET
Driver
FET
Driver
(1)
+
V
-
+
V
-
Period
(1)