PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 184

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
17.3
In Compare mode, the 16-bit value of the CCPRx
registers is constantly compared against either the
TMR1 or TMR3 register pair value. When a match
occurs, the CCPx pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
17.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 17-3:
DS39646B-page 182
I/O latch)
Note:
RG3/CCP4 pin
Compare Mode
CCPx PIN CONFIGURATION
Clearing the CCPxCON register will force
the compare output latch (depending on
device configuration) to the default low
level. This is not the port I/O data latch.
Output Enable
TRISG<3>
COMPARE MODE OPERATION BLOCK DIAGRAM
Q
R
S
Special Event Trigger
CCP4CON<3:0>
Mode Select
Output
Logic
Set Flag bit CCP4IF
Preliminary
Match
17.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
17.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
17.3.4
All CCP modules are equipped with a special event
trigger. This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The special event trigger is enabled by selecting
the
(CCPxM3:CCPxM0 = 1011).
For all CCP modules, the special event trigger resets the
timer register pair for whichever timer resource is cur-
rently assigned as the module’s time base. This allows
the CCPRx registers to serve as a programmable period
register for either timer.
The ECCP2 special event trigger can also start an A/D
conversion. In order to do this, the A/D converter must
already be enabled.
Compare
TMR1H
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
T3CCP2
TMR1L
Special
CCPR4H CCPR4L
Comparator
 2004 Microchip Technology Inc.
0
1
Event
TMR3H
Trigger
TMR3L
mode