PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 186

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
17.4
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 and CCP5 pins are multiplexed with a
PORTG data latch, the appropriate TRISG bit must be
cleared to make the CCP4 or CCP5 pin an output.
Figure 17-4 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up a CCP
module for PWM operation, see Section 17.4.3
“Setup for PWM Operation”.
FIGURE 17-4:
A PWM output (Figure 17-5) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
FIGURE 17-5:
DS39646B-page 184
Note 1: The 8-bit TMR2 or TMR4 value is concatenated with
Note:
CCPRxH (Slave)
TMR2 (TMR4)
Duty Cycle Registers
Comparator
PR2 (PR4)
CCPRxL
TMR2 (TMR4) = PR2 (TMR4)
Comparator
PWM Mode
the 2-bit internal Q clock, or 2 bits of the prescaler, to
create the 10-bit time base.
Duty Cycle
Clearing the CCP4CON or CCP5CON
register will force the RG3 or RG4 output
latch (depending on device configuration)
to the default low level. This is not the
PORTG I/O data latch.
Period
(Note 1)
TMR2 (TMR4) = Duty Cycle
Clear Timer,
CCPx pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 (TMR4) = PR2 (PR4)
CCPxCON<5:4>
R
S
Q
Corresponding
TRIS bit
CCPx Output
Preliminary
17.4.1
The PWM period is specified by writing to the PR2
(PR4) register. The PWM period can be calculated
using the following formula:
EQUATION 17-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 (TMR4) is equal to PR2 (PR4), the
following three events occur on the next increment
cycle:
• TMR2 (TMR4) is cleared
• The CCPx pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPRxL into
17.4.2
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 17-2:
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 (PR4) and
TMR2 (TMR4) occurs (i.e., the period is complete). In
PWM mode, CCPRxH is a read-only register.
cycle = 0%, the CCPx pin will not be set)
CCPRxH
Note:
PWM Duty Cycle = (CCPR
PWM Period = [(PR2) + 1] • 4 • T
PWM PERIOD
The Timer2 and Timer 4 postscalers (see
Section 14.0
Section 16.0 “Timer4 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
PWM DUTY CYCLE
T
(TMR2 Prescale Value)
OSC
 2004 Microchip Technology Inc.
“Timer2
• (TMR2 Prescale Value)
X
L:CCP
X
CON<5:4>) •
Module”
OSC
•
and