PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 148

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
11.5
PORTE is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting
a TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output
selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the device is operating in Microcontroller mode,
pin RE7 can be configured as the alternate peripheral
pin for the ECCP2 module. This is done by clearing the
CCP2MX configuration bit.
In 80-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled (80-pin
devices only), PORTE is the high-order byte of the
multiplexed address/data bus (AD15:AD8). The TRISE
bits are also overridden.
DS39646B-page 146
(i.e., put the contents of the output latch on the
Note:
PORTE, TRISE and
LATE Registers
On a Power-on Reset, these pins are
configured as digital inputs.
Preliminary
When the Parallel Slave Port is active on PORTD,
three
RE1/AD9/WR/P2C and RE2/AD10/CS/P2B) are config-
ured as digital control inputs for the port. The control
functions are summarized in Table 11-9. The reconfigu-
ration occurs automatically when the PSPMODE control
bit (PSPCON<4>) is set. Users must still make certain
the the corresponding TRISE bits are set to configure
these pins as digital inputs.
EXAMPLE 11-5:
CLRF
CLRF
MOVLW
MOVWF
of
PORTE
LATE
03h
TRISE
the
PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
INITIALIZING PORTE
 2004 Microchip Technology Inc.
pins
(RE0/AD8/RD/P2D,