PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 236
PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8722-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
70
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
128K Bytes
Ram Size
3.9K Bytes
Speed
40 MHz
Timers
2-8 bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Price
Company:
Part Number:
PIC18F8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
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Manufacturer:
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PIC18F8722 FAMILY
19.4.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPxADD<6:0> and
starts its count. If SCLx and SDAx are both sampled
high when the Baud Rate Generator times out (T
the SDAx pin is driven low. The action of the SDAx
being driven low while SCLx is high is the Start condi-
tion and causes the S bit (SSPxSTAT<3>) to be set.
Following this, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and resumes its
count. When the Baud Rate Generator times out
(T
matically cleared by hardware; the Baud Rate Generator
is suspended, leaving the SDAx line held low and the
Start condition is complete.
FIGURE 19-19:
DS39646B-page 234
BRG
), the SEN bit (SSPxCON2<0>) will be auto-
I
CONDITION TIMING
2
C MASTER MODE START
Write to SEN bit occurs here
FIRST START BIT TIMING
SDAx
SCLx
SDAx = 1,
SCLx = 1
T
BRG
BRG
Preliminary
),
Set S bit (SSPxSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
19.4.8.1
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write doesn’t occur).
and sets SSPxIF bit
Note:
Note:
Write to SSPxBUF occurs here
T
BRG
1st bit
If at the beginning of the Start condition,
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition, the
SCLx line is sampled low before the SDAx
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLxIF, is
set, the Start condition is aborted and the
I
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
2
C module is reset into its Idle state.
WCOL Status Flag
T
BRG
2004 Microchip Technology Inc.
2nd bit
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