PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 442

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
Timer0 .............................................................................. 161
Timer1 .............................................................................. 165
Timer2 .............................................................................. 171
Timer3 .............................................................................. 173
Timer4 .............................................................................. 177
Timing Diagrams
DS39646B-page 440
Associated Registers ............................................... 163
Operation ................................................................. 162
Overflow Interrupt .................................................... 163
Prescaler .................................................................. 163
Prescaler Assignment (PSA Bit) .............................. 163
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 163
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 162
Source Edge Select (T0SE Bit) ................................ 162
Source Select (T0CS Bit) ......................................... 162
Switching Prescaler Assignment .............................. 163
16-Bit Read/Write Mode ........................................... 167
Associated Registers ............................................... 169
Interrupt .................................................................... 168
Operation ................................................................. 166
Oscillator .......................................................... 165, 167
Overflow Interrupt .................................................... 165
Resetting, Using the CCP
Special Event Trigger (ECCP) ................................. 192
TMR1H Register ...................................................... 165
TMR1L Register ....................................................... 165
Use as a Real-Time Clock ....................................... 168
Associated Registers ............................................... 172
Interrupt .................................................................... 172
Operation ................................................................. 171
Output ...................................................................... 172
PR2 Register .................................................... 184, 192
TMR2 to PR2 Match Interrupt .......................... 184, 192
16-Bit Read/Write Mode ........................................... 175
Associated Registers ............................................... 175
Operation ................................................................. 174
Oscillator .......................................................... 173, 175
Overflow Interrupt ............................................ 173, 175
Special Event Trigger (CCP) .................................... 175
TMR3H Register ...................................................... 173
TMR3L Register ....................................................... 173
Associated Registers ............................................... 178
MSSP Clock Shift ..................................................... 178
Operation ................................................................. 177
Postscaler. See Postscaler, Timer4.
PR4 Register ............................................................ 177
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 177
TMR4 to PR4 Match Interrupt .......................... 177, 178
A/D Conversion ........................................................ 418
Asynchronous Reception ......................................... 261
Asynchronous Transmission .................................... 258
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 256
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 262
Baud Rate Generator with
BRG Overflow Sequence ......................................... 256
BRG Reset Due to SDAx Arbitration
Layout Considerations ..................................... 168
Special Event Trigger ....................................... 168
(Back to Back) .................................................. 258
Normal Operation ............................................. 262
Clock Arbitration ............................................... 233
During Start Condition ...................................... 242
Preliminary
Brown-out Reset (BOR) ........................................... 405
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision for Transmit and
Capture/Compare/PWM
CLKO and I/O .......................................................... 402
Clock Synchronization ............................................. 226
Clock/Instruction Cycle .............................................. 69
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 409
Example SPI Master Mode (CKE = 1) ..................... 410
Example SPI Slave Mode (CKE = 0) ....................... 411
Example SPI Slave Mode (CKE = 1) ....................... 412
External Clock (All Modes Except PLL) ................... 400
External Memory Bus for Sleep
External Memory Bus for TBLRD
External Memory Bus for TBLRD
External Memory Bus for TBLRD with 1 T
Fail-Safe Clock Monitor (FSCM) .............................. 316
First Start Bit Timing ................................................ 234
Full-Bridge PWM Output .......................................... 197
Half-Bridge PWM Output ......................................... 196
High/Low-Voltage Detect Characteristics ................ 397
High-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation
Master SSP I
Master SSP I
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence .................................... 239
C Bus Data ............................................................ 413
C Bus Start/Stop Bits ............................................ 413
C Master Mode (7 or
C Master Mode (7-Bit Reception) .......................... 238
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Transmission) .................... 224
C Slave Mode (7-bit Reception, SEN = 0) ............ 221
C Slave Mode (7-Bit Reception, SEN = 1) ............ 227
C Slave Mode (7-Bit Transmission) ...................... 222
C Slave Mode General Call Address
C Stop Condition Receive or
Start Condition (Case 1) .................................. 243
Start Condition (Case 2) .................................. 243
(SCLx = 0) ....................................................... 242
(Case 1) ........................................................... 244
(Case 2) ........................................................... 244
(SDAx Only) ..................................................... 241
Acknowledge ................................................... 240
(All ECCP/CCP Modules) ................................ 407
(Master/Slave) ................................................. 417
(Master/Slave) ................................................. 417
(Microprocessor Mode) ............................ 105, 108
(Extended Microcontroller Mode) ............ 104, 107
(Microprocessor Mode) .................................... 107
Wait State (Microprocessor Mode) .................. 104
(VDIRMAG = 1) ............................................... 294
10-Bit Transmission) ........................................ 237
SEN = 0) .......................................................... 223
SEN = 1) .......................................................... 228
Sequence (7 or 10-Bit Address Mode) ............ 229
Transmit Mode ................................................. 239
(VDIRMAG = 0) ............................................... 293
2
2
C Bus Data ........................................ 415
C Bus Start/Stop Bits ........................ 415
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