PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 436

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
F
Fail-Safe Clock Monitor ............................................ 297, 315
Fast Register Stack ............................................................ 68
Firmware Instructions ....................................................... 321
Flash Program Memory ...................................................... 87
FSCM. See Fail-Safe Clock Monitor.
G
General Call Address Support ......................................... 229
GOTO ............................................................................... 342
H
Hardware Multiplier .......................................................... 117
High/Low-Voltage Detect ................................................. 291
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 135
I
DS39646B-page 434
2
C Mode (MSSP)
Exiting Operation ..................................................... 315
Interrupts in Power-Managed Modes ....................... 316
POR or Wake from Sleep ........................................ 316
WDT During Oscillator Failure ................................. 315
Associated Registers ................................................. 95
Control Registers ....................................................... 88
Erase Sequence ........................................................ 92
Erasing ....................................................................... 92
Operation During Code-Protect ................................. 95
Reading ...................................................................... 91
Table Pointer
Table Pointer Boundaries .......................................... 90
Table Reads and Table Writes .................................. 87
Write Sequence ......................................................... 93
Writing To ................................................................... 93
Introduction .............................................................. 117
Operation ................................................................. 117
Performance Comparison ........................................ 117
Applications .............................................................. 294
Associated Registers ............................................... 295
Characteristics ......................................................... 397
Current Consumption ............................................... 293
Effects of a Reset ..................................................... 295
Operation ................................................................. 292
Setup ........................................................................ 293
Start-up Time ........................................................... 293
Typical Application ................................................... 294
Acknowledge Sequence Timing ............................... 239
Associated Registers ............................................... 245
Baud Rate Generator ............................................... 232
Bus Collision
Clock Arbitration ....................................................... 233
EECON1 and EECON2 ..................................... 88
TABLAT (Table Latch) Register ......................... 90
TBLPTR (Table Pointer) Register ...................... 90
Boundaries Based on Operation ........................ 90
Protection Against Spurious Writes ................... 95
Unexpected Termination .................................... 95
Write Verify ........................................................ 95
During Sleep .................................................... 295
During a Repeated Start Condition .................. 243
During a Stop Condition ................................... 244
Preliminary
ID Locations ............................................................. 297, 320
INCF ................................................................................ 342
INCFSZ ............................................................................ 343
In-Circuit Debugger .......................................................... 320
In-Circuit Serial Programming (ICSP) ...................... 297, 320
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 368
Indirect Addressing ............................................................ 82
INFSNZ ............................................................................ 343
Initialization Conditions for all Registers ...................... 57–61
Instruction Cycle ................................................................ 69
Instruction Flow/Pipelining ................................................. 69
Instruction Set .................................................................. 321
Clock Stretching ....................................................... 225
Clock Synchronization and the CKP bit ................... 226
Effects of a Reset .................................................... 240
General Call Address Support ................................. 229
I
Master Mode ............................................................ 230
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 240
Operation ................................................................. 219
Read/Write Bit Information (R/W Bit) ............... 219, 220
Registers ................................................................. 215
Serial Clock (RC3/SCKx/SCLx) ............................... 220
Slave Mode .............................................................. 219
Sleep Operation ....................................................... 240
Stop Condition Timing ............................................. 239
and Standard PIC18 Instructions ............................. 368
Clocking Scheme ....................................................... 69
ADDLW .................................................................... 327
ADDWF .................................................................... 327
ADDWF (Indexed Literal Offset Mode) .................... 369
ADDWFC ................................................................. 328
ANDLW .................................................................... 328
ANDWF .................................................................... 329
BC ............................................................................ 329
BCF ......................................................................... 330
BN ............................................................................ 330
BNC ......................................................................... 331
BNN ......................................................................... 331
BNOV ...................................................................... 332
BNZ ......................................................................... 332
BOV ......................................................................... 335
BRA ......................................................................... 333
BSF .......................................................................... 333
BSF (Indexed Literal Offset Mode) .......................... 369
BTFSC ..................................................................... 334
2
C Clock Rate w/BRG ............................................. 232
10-Bit Slave Receive Mode (SEN = 1) ............ 225
10-Bit Slave Transmit Mode ............................ 225
7-Bit Slave Receive Mode (SEN = 1) .............. 225
7-Bit Slave Transmit Mode .............................. 225
Operation ......................................................... 231
Reception ........................................................ 236
Repeated Start Condition Timing .................... 235
Start Condition Timing ..................................... 234
Transmission ................................................... 236
and Arbitration ................................................. 240
Addressing ....................................................... 219
Reception ........................................................ 220
Transmission ................................................... 220
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