PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 157

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 11-15: PORTH FUNCTIONS
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
 2004 Microchip Technology Inc.
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RH4/AN12/
P3C
RH5/AN13/
P3B
RH6/AN14/
P1C
RH7/AN15/
P1B
Legend:
Note 1:
TRISH
PORTH
LATH
ADCON1
Pin Name
Name
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
Function
TRISH7
LATH7
P3C
P1C
P3B
P1B
AN12
AN13
AN14
AN15
Bit 7
RH0
RH1
RH2
RH3
RH4
RH5
RH6
RH7
RH7
A16
A17
A18
A19
—
(1)
(1)
(1)
(1)
Setting
TRISH6
TRIS
LATH6
Bit 6
RH6
0
1
x
0
1
x
0
1
x
0
1
x
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
—
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
TRISH5
VCFG1
LATH5
Bit 5
RH5
Type
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
TRISH4
VCFG0
Preliminary
LATH4
LATH<0> data output.
PORTH<0> data input.
External memory interface, address line 16. Takes priority over port data.
LATH<1> data output.
PORTH<1> data input.
External memory interface, address line 17. Takes priority over port data.
LATH<2> data output.
PORTH<2> data input.
External memory interface, address line 18. Takes priority over port data.
LATH<3> data output.
PORTH<3> data input.
External memory interface, address line 19. Takes priority over port data.
LATH<4> data output.
PORTH<4> data input.
A/D input channel 12. Default configuration on POR.
ECCP3 Enhanced PWM output, channel C. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
LATH<5> data output.
PORTH<5> data input.
A/D input channel 13. Default configuration on POR.
ECCP3 Enhanced PWM output, channel B. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
LATH<6> data output.
PORTH<6> data input.
A/D input channel 14. Default configuration on POR.
ECCP1 Enhanced PWM output, channel C. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
LATH<7> data output.
PORTH<7> data input.
A/D input channel 15. Default configuration on POR.
ECCP1 Enhanced PWM output, channel B. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
Bit 4
RH4
TRISH3
PCFG3
LATH3
Bit 3
RH3
PIC18F8722 FAMILY
TRISH2
PCFG2
LATH2
Bit 2
RH2
Description
TRISH1
PCFG1
LATH1
Bit 1
RH1
TRISH0
PCFG0
LATH0
Bit 0
RH0
DS39646B-page 155
on page
Values
Reset
60
60
60
59