PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 101

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.2
PIC18F8527/8622/8627/8722 devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by configuration bits in the CONFIG3L register.
As configuration bits, this means that these options can
only be configured by programming the device and are
not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The ADW1:ADW0 bits determine the address bus
width. The available options are 20-bit (default), 16-bit,
12-bit and 8-bit. Selecting any of the options other than
20-bit width makes a corresponding number of
high-order lines available for I/O functions; these pins
are no longer affected by the setting of the EBDIS bit.
For example, selecting a 16-bit Address mode
(ADW1:ADW0 = 10) disables A19:A16 and allows
PORTH<3:0> to function without interruptions from the
bus. Using smaller address widths allows users to tailor
the memory bus to the size of the external memory
space for a particular design while freeing up pins for
dedicated I/O operation.
Because the ADW bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If 8-bit or 12-bit address widths are used with a 16-bit
data width, the upper bits of data will not be available
on the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
TABLE 7-2:
 2004 Microchip Technology Inc.
Data Width
16-bit
8-bit
Address and Data Width
ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Address Width
12-bit
16-bit
20-bit
16-bit
20-bit
8-bit
Corresponding Ports)
Multiplexed Data and
Address Lines (and
(PORTD<7:0>)
(PORTD<7:0>,
PORTE<7:0>)
Preliminary
AD15:AD0
AD7:AD0
7.2.1
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2 Mbyte
memory space. This is done by using the Bus Address
bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
This addressing mode is available in both 8-bit and
certain 16-bit Data Width modes. Additional details are
provided in Section 7.5.3 “16-bit Byte Select Mode”
and Section 7.6 “8-bit Data Width Modes”.
7.3
While it may be assumed that external memory devices
will operate at the microcontroller clock rate, this is
often not the case. In fact, many devices require longer
times to write or retrieve data than the time allowed by
the execution of table read or table write operations.
To compensate for this, the external memory bus can
be configured to add a fixed delay to each table opera-
tion using the bus. Wait states are enabled by setting
the WAIT configuration bit. When enabled, the amount
of
(MEMCON<5:4>). The delay is based on multiples of
microcontroller instruction cycle time and are added
following the instruction cycle when the table operation
is executed. The range is from no delay to 3 T
(default value).
PIC18F8722 FAMILY
delay
Corresponding Ports)
A19:A16, AD15:AD8
Wait States
(PORTE<3:0>)
(PORTE<7:0>)
(PORTH<3:0>,
(PORTH<3:0>)
Address-Only
21-BIT ADDRESSING
PORTE<7:0>)
is
Lines (and
AD15:AD8
AD11:AD8
A19:A16
set
—
—
by
the
WAIT1:WAIT0
All of PORTE and
Ports Available
PORTE<7:4>,
All of PORTH
All of PORTH
All of PORTH
DS39646B-page 99
PORTH
for I/O
—
—
bits
CY