PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 241

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into an inactive state
(Figure 19-23).
19.4.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 19-23:
FIGURE 19-24:
 2004 Microchip Technology Inc.
BRG
) and the SCLx pin is deasserted (pulled high).
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCLx
SDAx
Note: T
Sequence
Note: T
Write to SSPxCON2,
SSPxIF
SDAx
SCLx
Falling edge of
9th clock
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
Acknowledge sequence starts here,
ACK
= one Baud Rate Generator period.
= one Baud Rate Generator period.
SSPxIF set at
the end of receive
set PEN
Enable
ACKEN = 1, ACKDT = 0
write to SSPxCON2,
BRG
T
T
. The SCLx pin
bit,
BRG
BRG
SDAx asserted low before rising edge of clock
to setup Stop condition
D0
8
ACKEN
T
SCLx brought high after T
BRG
Preliminary
Cleared in
software
P
T
BRG
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
T
BRG
ACK
19.4.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
cleared and the SSPxIF bit is set (Figure 19-24).
19.4.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
PIC18F8722 FAMILY
T
PEN bit (SSPxCON2<2>) is cleared by
BRG
hardware and the SSPxIF bit is set
9
BRG
SSPxIF set at the end
of Acknowledge sequence
BRG
, followed by SDAx = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
Cleared in
software
BRG
BRG
later, the PEN bit is
DS39646B-page 239