PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 282

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
21.8
An A/D conversion can be started by the special event
trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
TABLE 21-2:
DS39646B-page 280
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
TRISA
TRISF
TRISH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
2:
(2)
Use of the ECCP2 Trigger
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
These registers are not implemented on 64-pin devices.
TRISA7
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
OSCFIE
OSCFIP
OSCFIF
TRISH7
TRISF7
PSPIF
PSPIE
PSPIP
ADFM
Bit 7
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
bits
TRISA6
TRISH6
TRISF6
CMIF
CMIE
CMIP
ADIE
ADIP
ADIF
Bit 6
—
—
—
(CCP2CON<3:0>)
(1)
TRISH5
TRISA5
TRISF5
VCFG1
ACQT2
RC1IF
RC1IE
RC1IP
CHS3
Bit 5
—
—
—
TRISH4
TRISA4
TRISF4
VCFG0
ACQT1
INT0IE
Preliminary
TX1IF
TX1IE
TX1IP
CHS2
EEIF
EEIE
EEIP
be
Bit 4
SSP1IE
SSP1IP
TRISA3
TRISH3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
TRISF3
PCFG3
ACQT0
CHS1
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
special event trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
RBIE
Bit 3
ACQ
time selected before the special event trigger sets
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISH2
HLVDIF
HLVDIE
HLVDIP
TRISA2
TRISF2
PCFG2
ADCS2
CHS0
Bit 2
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISA1
TRISF1
TRISH1
PCFG1
ADCS1
INT0IF
Bit 1
 2004 Microchip Technology Inc.
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP2IF
TRISA0
TRISF0
TRISH0
PCFG0
ADCS0
ADON
RBIF
Bit 0
on page
Values
Reset
57
60
60
60
60
60
60
59
59
59
59
59
60
60
60