PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 202

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
18.4.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current
(shoot-through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally program-
mable dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transi-
tion from the non-active state to the active state. See
Figure 18-4 for illustration. The lower seven bits of the
ECCP1DEL register (Register 18-2) set the delay
period in terms of microcontroller instruction cycles
(T
18.4.7
When the ECCP is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
REGISTER 18-2:
DS39646B-page 200
CY
or 4 T
OSC
bit 7
bit 6-0
PROGRAMMABLE DEAD-BAND
DELAY
ENHANCED PWM
AUTO-SHUTDOWN
).
ECCPxDEL: ENHANCED PWM CONFIGURATION REGISTER
bit 7
PxRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, the ECCPxASE bit must be cleared in software to restart the PWM
PxDC6:PxDC0: PWM Delay Count bits
Delay time, in number of F
a PWM signal to transition to active.
Legend:
R = Readable bit
-n = Value at POR
PxRSEN
R/W-0
goes away; the PWM restarts automatically
PxDC6
R/W-0
PxDC5
R/W-0
OSC
Preliminary
W = Writable bit
‘1’ = Bit is set
/4 (4 * T
PxDC4
R/W-0
OSC
A shutdown event can be caused by either of the two
comparator modules or the FLT0 pin (or any combina-
tion of these three sources). The comparators may be
used to monitor a voltage input proportional to a current
being monitored in the bridge circuit. If the voltage
exceeds a threshold, the comparator switches state and
triggers a shutdown. Alternatively, a digital signal on the
FLT0
auto-shutdown feature can be disabled by not selecting
any auto-shutdown sources. The auto-shutdown
sources
ECCP1AS2:ECCP1AS0 bits (ECCP1AS<6:4>).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
PSS1BD1:PSS1BD0 bits (ECCP1AS<3:0>). Each pin
pair (P1A/P1C and P1B/P1D) may be set to drive high,
drive low or be tri-stated (not driving). The ECCP1ASE
bit (ECCP1AS<7>) is also set to hold the Enhanced
PWM outputs in their shutdown states.
The ECCP1ASE bit is set by hardware when a shut-
down event occurs. If automatic restarts are not
enabled, the ECCP1ASE bit is cleared by firmware
when the cause of the shutdown clears. If automatic
restarts are enabled, the ECCP1ASE bit is auto-
matically cleared when the cause of the auto-shutdown
has cleared.
If the ECCP1ASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCP1ASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
) cycles, between the scheduled and actual time for
pin
PxDC3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
to
Writing to the ECCP1ASE bit is disabled
while a shutdown condition is active.
by
can
be
the
also
used
PxDC2
R/W-0
 2004 Microchip Technology Inc.
trigger
PSS1AC1:PSS1AC0
are
x = Bit is unknown
selected
PxDC1
R/W-0
a
shutdown.
using
PxDC0
R/W-0
bit 0
The
and
the