PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 111
PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8722-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
70
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
128K Bytes
Ram Size
3.9K Bytes
Speed
40 MHz
Timers
2-8 bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8722-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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7.7
In alternate power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
TABLE 7-3:
2004 Microchip Technology Inc.
MEMCON
CONFIG3L
CONFIG3H
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the external memory bus.
Note 1:
Name
2:
Operation in Power-Managed
Modes
(1)
This register is not implemented on 64-pin devices.
Unimplemented in PIC18F6527/6622/6627/6722 devices.
(2)
MCLRE
EBDIS
WAIT
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-MANAGED MODES
Bit 6
BW
—
—
WAIT1
ABW1
Bit 5
—
Preliminary
WAIT0
ABW0
Bit 4
—
Bit 3
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are sus-
pended. The state of the external bus is frozen with the
address/data pins and most of the control pins holding
at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins which are held at logic high.
—
—
—
PIC18F8722 FAMILY
LPT1OSC ECCPMX
Bit 2
—
—
WM1
Bit 1
PM1
(2)
CCP2MX
WM0
Bit 0
PM0
DS39646B-page 109
on page
Values
Reset
302
303
60
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