PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 54

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
4.4
The PIC18F8722 family of devices implements a BOR
circuit that provides the user with a number of con-
figuration and power-saving options. The BOR is con-
trolled by the BORV1:BORV0 and BOREN1:BOREN0
configuration bits. There are a total of four BOR
configurations which are summarized in Table 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any values of BOREN1:BOREN0,
except ‘00’), any drop of V
D005, Section 28.1 “DC Characteristics”) for greater
than T
device. A Reset may or may not occur if V
V
Brown-out Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset
(parameter 33, Table 28-12). If V
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once V
Power-up Timer will execute the additional time delay.
BOR
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
4.4.1
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
TABLE 4-1:
DS39646B-page 52
BOR
DD
BOREN1
BOR Configuration
rises above V
0
0
1
1
BOR
for less than T
and
for
Brown-out Reset (BOR)
(parameter 35, Table 28-12) will reset the
SOFTWARE ENABLED BOR
an
the
BOREN0
BOR CONFIGURATIONS
additional
Power-on
BOR
0
1
0
1
BOR
; it then will keep the chip in
DD
DD
. The chip will remain in
DD
rises above V
(RCON<6>)
Unavailable
Unavailable
Unavailable
SBOREN
below V
Available
Status of
rises above V
time
Timer
DD
drops below V
delay,
BOR
(PWRT)
DD
BOR
(parameter
BOR disabled; must be enabled by reprogramming the configuration bits.
BOR enabled in software; operation controlled by SBOREN.
BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
BOR enabled in hardware; must be disabled by reprogramming the
configuration bits.
falls below
.
BOR
T
PWRT
, the
BOR
Preliminary
are
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor device power consumption in software by
eliminating the incremental current that the BOR con-
sumes. While the BOR current is typically very small, it
may have some impact in low-power applications.
4.4.2
When BOR is enabled, the BOR bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any POR event. If BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a BOR event
has occurred.
4.4.3
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
BOR Operation
Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV1:BORV0 configuration bits. It
cannot be changed in software.
DETECTING BOR
DISABLING BOR IN SLEEP MODE
 2004 Microchip Technology Inc.