PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 70

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
5.1.3.4
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.4
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no inter-
rupts are used, the fast register stack can be used to
restore the STATUS, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALL label, FAST instruction
must be executed to save the STATUS, WREG and
BSR
RETURN, FAST instruction is then executed to restore
these registers from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and return.
EXAMPLE 5-2:
DS39646B-page 68
MAIN: ORG
…
TABLE MOVF
registers
MOVLW 0x00
CALL
ORG
RLNCF W, W
ADDWF PCL
RETLW ‘A’
RETLW ‘B’
RETLW ‘C’
RETLW ‘D’
RETLW ‘E’
END
FAST REGISTER STACK
Stack Full and Underflow Resets
0x0000
TABLE
0x8000
PCL, F
to
the
COMPUTED GOTO USING AN OFFSET VALUE
fast
; A simple read of PCL will update PCLATH, PCLATU
; Multiply by 2 to get correct offset in table
; Add the modified offset to force jump into table
register
stack.
Preliminary
A
EXAMPLE 5-1:
5.1.5
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.5.1
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF
instruction and a group of RETLW nn instructions. The W
register is loaded with an offset into the table before exe-
cuting a call to that table. The first instruction of the called
routine is the ADDWF PCL instruction. The next instruction
executed will be one of the RETLW nn instructions that
returns the value ‘nn’ to the calling function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
CALL SUB1, FAST
SUB1
Note:
RETURN, FAST
•
•
•
•
LOOK-UP TABLES IN PROGRAM
MEMORY
The “ADDWF
update the PCLATH and PCLATU registers.
A read operation on PCL must be performed
to update PCLATH and PCLATU.
Computed GOTO
FAST REGISTER STACK
CODE EXAMPLE
 2004 Microchip Technology Inc.
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
PCL” instruction does not
PCL