PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 306

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
REGISTER 25-6:
DS39646B-page 304
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
BBSIZ<1:0>: Boot Block Size Select bits
11 = 4K words (8 Kbytes) Boot Block size
10 = 4K words (8 Kbytes) Boot Block size
01 = 2K words (4 Kbytes) Boot Block size
00 = 1K word (2 Kbytes) Boot Block size
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
Legend:
R = Readable bit
-n = Value when device is unprogrammed
DEBUG
R/P-1
XINST
R/P-0
C = Clearable bit
BBSIZ1
R/P-0
Preliminary
BBSIZ0
R/P-0
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
—
R/P-1
LVP
 2004 Microchip Technology Inc.
U-0
—
STVREN
R/P-1
bit 0