PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 150

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F8722 FAMILY
TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39646B-page 148
RE5/AD13/P1C
RE6/AD14/P1B
RE7/AD15/
ECCP2/P2A
Legend:
Note 1:
PORTE
LATE
TRISE
Name
Pin Name
2:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode).
Implemented on 80-pin devices only.
TRISE7
LATE7
Bit 7
RE7
Function
ECCP2
PORTE FUNCTIONS (CONTINUED)
AD13
AD14
AD15
P2A
RE5
P1C
RE6
RE7
P1B
(1)
(2)
(2)
(2)
(1)
TRISE6
LATE6
Bit 6
RE6
Setting
TRIS
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
1
0
TRISE5
LATE5
Bit 5
RE5
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
TRISE4
LATE4
Preliminary
Bit 4
RE4
LATE<5> data output.
PORTE<5> data input.
External memory interface, address/data bit 13 output. Takes priority
over ECCP and port data.
External memory interface, data bit 13 input.
ECCP1 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<6> data output.
PORTE<6> data input.
External memory interface, address/data bit 14 output. Takes priority
over ECCP and port data.
External memory interface, data bit 14 input.
ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<7> data output.
PORTE<7> data input.
External memory interface, address/data bit 15 output. Takes priority
over ECCP and port data.
External memory interface, data bit 15 input.
ECCP2 compare output and ECCP2 PWM output. Takes priority over
port data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, channel A. Takes priority over port and
data. May be configured for tri-state during Enhanced PWM shutdown
events.
TRISE3
LATE3
Bit 3
RE3
TRISE2
LATE2
Bit 2
RE2
Description
TRISE1
LATE1
Bit 1
 2004 Microchip Technology Inc.
RE1
TRISE0
LATE0
Bit 0
RE0
on page
Values
Reset
60
60
60