PIC18F8722-I/PT Microchip Technology Inc., PIC18F8722-I/PT Datasheet - Page 77

• Manufacturer Part Number: PIC18F8722-I/PT
• Description: 80 PIN, 128 KB FLASH, 4K RAM, 70 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8722-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 70
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 3.9K Bytes
• Speed: 40 MHz
• Timers: 2-8 bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F60h to FFFh). A list of these
registers is given in Table 5-2 and Table 5-3.
TABLE 5-2:
 2004 Microchip Technology Inc.
Note 1:
Address
FFDh
FFCh
FEEh POSTINC0
FEDh POSTDEC0
FECh
FEBh
FEAh
FFEh
FFBh
FEFh
FFFh
FFAh
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
2:
3:
PREINC0
PREINC1
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 64-pin devices.
SPECIAL FUNCTION REGISTERS
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
TOSU
TOSH
Name
TOSL
BSR
PCL
SPECIAL FUNCTION REGISTER MAP FOR THE PIC18F8722 FAMILY OF DEVICES
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDEh POSTINC2
FDDh POSTDEC2
FDCh
FDBh
FDAh
FCEh
FCDh
FCCh
FCBh
FCAh
FDFh
FCFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
SSP1CON1
SSP1CON2
PLUSW2
SSP1STAT
HLVDCON
SSP1ADD
WDTCON
SSP1BUF
OSCCON
ADRESH
ADCON0
ADCON1
ADCON2
ADRESL
INDF2
STATUS
TMR0H
TMR1H
T0CON
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
—
PR2
(2)
(1)
(1)
(1)
(1)
(1)
Address
Preliminary
FBDh
FBCh
FBFh
FBEh
FBBh
FBAh
FADh
FACh
FABh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
EECON2
CCP1CON
CCP2CON
CCP3CON
ECCP1AS
CVRCON
PSPCON
CCPR1H
CCPR2H
CCPR3H
SPBRG1
RCREG1
TXREG1
EEADRH
EECON1
CCPR1L
CCPR2L
CCPR3L
RCSTA1
EEDATA
CMCON
TXSTA1
TMR3H
EEADR
TMR3L
T3CON
Name
IPR3
PIR3
IPR2
PIR2
PIE3
PIE2
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this sec-
tion. Registers related to the operation of a peripheral
feature are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
PIC18F8722 FAMILY
(1)
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F98h
F91h
F90h
F8Fh
F86h
F85h
F84h
F82h
F81h
F80h
F99h
F97h
F96h
F95h
F94h
F93h
F92h
F89h
F88h
F87h
F83h
OSCTUNE
MEMCON
PORTH
PORTJ
TRISH
TRISJ
PORTG
LATH
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
LATJ
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
Name
LATG
LATD
LATC
LATF
LATE
LATB
LATA
IPR1
PIR1
PIE1
(3)
(3)
(3)
(3)
(3)
(3)
Address
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F7Fh
F6Fh
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
DS39646B-page 75
BAUDCON1
BAUDCON2
ECCP1DEL
ECCP3DEL
ECCP2DEL
SSP2CON1
SSP2CON2
SSP2STAT
CCP4CON
CCP5CON
SPBRGH1
SPBRGH2
ECCP3AS
ECCP2AS
SSP2ADD
SSP2BUF
CCPR4H
CCPR5H
SPBRG2
RCREG2
CCPR4L
CCPR5L
TXREG2
RCSTA2
TXSTA2
T4CON
Name
TMR4
—
—
PR4
—
—
(2)
(2)
(2)
(2)