TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 15

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11. Serial Bus Interface (I2C/SIO)
10.12 Transmission......................................................................................................................246
10.13 Handshake function...........................................................................................................250
10.14 Interrupt/Error Generation Timing....................................................................................251
10.15 Software Reset...................................................................................................................253
10.16 Operation in Each Mode....................................................................................................254
11.1 Configuration.......................................................................................................................270
11.2 Register................................................................................................................................271
11.3 I2C Bus Mode Data Format.................................................................................................272
11.4 Control Registers in the I2C Bus Mode...............................................................................273
11.5 Control in the I2C Bus Mode...............................................................................................280
10.12.1
10.12.2
10.12.3
10.14.1
10.14.2
10.14.3
10.16.1
10.16.2
10.16.3
10.16.4
11.2.1
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.8
11.5.9
10.11.3.1
10.11.3.2
10.11.3.3
10.11.3.4
10.11.3.5
10.11.3.6
10.12.2.1
10.12.2.2
10.12.3.1
10.12.3.2
10.12.3.3
10.12.3.4
10.14.1.1
10.14.1.2
10.14.2.1
10.14.2.2
10.14.3.1
10.14.3.2
10.16.1.1
10.16.1.2
10.16.1.3
10.16.4.1
10.16.4.2
11.5.1.1
11.5.1.2
Registers for each channel.............................................................................................................................................271
SBIxCR0(Control register 0).........................................................................................................................................273
SBIxCR1(Control register 1).........................................................................................................................................274
SBIxCR2(Control register 2).........................................................................................................................................276
SBIxSR (Status Register)...............................................................................................................................................277
SBIxBR0(Serial bus interface baud rate register 0).......................................................................................................278
SBIxDBR (Serial bus interface data buffer register).....................................................................................................278
SBIxI2CAR (I2Cbus address register)..........................................................................................................................279
Serial Clock....................................................................................................................................................................280
Setting the Acknowledgement Mode.............................................................................................................................281
Setting the Number of Bits per Transfer........................................................................................................................281
Slave Addressing and Address Recognition Mode........................................................................................................281
Operating mode..............................................................................................................................................................281
Configuring the SBI as a Transmitter or a Receiver......................................................................................................282
Configuring the SBI as a Master or a Slave...................................................................................................................282
Generating Start and Stop Conditions...........................................................................................................................282
Interrupt Service Request and Release..........................................................................................................................283
Transmission Counter..................................................................................................................................................246
Transmission Control...................................................................................................................................................246
Transmit Operation......................................................................................................................................................246
RX Interrupts...............................................................................................................................................................251
TX interrupts................................................................................................................................................................252
Error Generation..........................................................................................................................................................253
Mode 0 (I/O interface mode).......................................................................................................................................254
Mode 1 (7-bit UART mode)........................................................................................................................................265
Mode 2 (8-bit UART mode)........................................................................................................................................265
Mode 3 (9-bit UART mode)........................................................................................................................................266
Clock source
Clock Synchronization
Receive Buffer
Receive FIFO Operation
I/O interface mode with SCLK output
Read Received Data
Wake-up Function
Overrun Error
I/O Interface Mode
UART Mode
Operation of Transmission Buffer
Transmit FIFO Operation
I/O interface Mode/Transmission by SCLK Output
Under-run error
Single Buffer / Double Buffer
FIFO
Single Buffer / Double Buffer
FIFO
UART Mode
IO Interface Mode
Transmitting Data
Receive
Transmit and Receive (Full-duplex)
Wakeup function
Protocol
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