TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 263

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

RX FIFO
10.11.3.2
RX Interrupt (INTRXx)
SCxMOD2<RBFLL>
Receive shift register
SCxMOD0<RXE>
The second stage
The fourth stage
The third stage
Receive buffer
The first stage
buffer full flag is cleared immediately. An interrupt will be generated according to the SCxRFC<RIL> setting.
<RXE>. When the data is stored all in the receive shift register, receive buffer and receive FIFO,
SCxMOD0<RXE> is automatically cleared and the receive operation is finished.
to receive a data continuouslywith and reading the data in the FIFO.
When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and the receive
The following describes configurations and operations in the half duplex RX mode.
After setting of the above FIFO configuration, the data reception is started by writing "1" to the SCxMOD0
In this above condition, if the cotinuous reception after reaching the fill level is enabed, and it is possible
Note:When the data with parity bit are received in UART mode by using the FIFO, the parity error flag is
Receive FIFO Operation
SCxMOD1[6:5] =01
SCxFCNF[4:0] = 10111
SCxRFC[1:0] = 00
SCxRFC[7:6] = 11
shown the occurring the parity error in the received data.
DATA1
Figure 10-5 Receive FIFO Operation
: Transfer mode is set to half duplex mode
: Automatically inhibits continuous reception after reaching the fill level.
: The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill level.
: The fill level of FIFO in which generated receive interrupt is set to 4-byte.
: Clears receive FIFO and sets the condition of interrupt generation.
DATA2
DATA1
DATA1
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DATA3
DATA2
DATA2
DATA1
DATA4
DATA3
DATA3
DATA2
DATA1
DATA5
DATA4
DATA4
DATA3
DATA2
DATA1
TMPM333FDFG/FYFG/FWFG
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA5
DATA4
DATA3
DATA2
DATA1