TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 325

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

INTSBIx
interrupt request
11.8.2.2
<SIOS>
<SIOF>
<SEF>
SCKx pin(Output)
SIx pin
SBIxDBR
INTSBIx interrupt
SBIxCR1
SBIxCR1
Reg.
is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchronization
with the serial clock. Once the shift register is loaded with the 8-bit data, it transfers the received data to
SBIxDBR and the INTSBIx (buffer-full) interrupt request is generated to request reading the received data.
The interrupt service program then reads the received data from SBIxDBR.
received data is read from SBIxDBR.
maximum data transfer rate varies, depending on the maximum latency between generating the interrupt
request and reading the received data
interrupt service program. If <SIOS> is cleared, reception continues until all the bits of received data are
written to SBIxDBR. The program checks SBIxSR<SIOF> to determine whether reception has come to an
end.<SIOF> is cleared to "0" at the end of reception. After confirming the completion of the reception, last
received data is read. If <SIOINH> is set to "1", the reception is aborted immediately and <SIOF> is cleared
to "0". (The received data becomes invalid, and there is no need to read it out.)
Set the control register to the receive mode. Then writing "1" to SBIxCR1<SIOS> enables reception.Data
In the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the
In the external clock mode, shift operations are executed in synchronization with the external clock. The
Reception can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the INTSBIx
Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing
8-bit receive mode
reception must be completed by clearing <SIOS> to "0" and the last received data must be read
before the transfer mode is changed.
←
←
←
Figure 11-19 Receive Mode (Example: Internal Clock)
7
0
1
SBIxDBR
a
0
6
1
0
a
5
1
1
1
a
4
1
1
2
3
0
0
a
3
2
X
X
a
4
1
X
X
Page 305
a
5
0
X
X
a
6
Read receive data
a
Selects the receive mode.
Starts reception.
Reads the received data.
7
a
b
0
b
1
b
2
Clear <SIOS>
b
3
TMPM333FDFG/FYFG/FWFG
b
4
b
5
b
6
Read receive data
b
7
b