TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 164

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

8.2
Port functions
8.2.10
Type
8.2.10.1
8.2.10.2
units of bits. Besides the general-purpose port function, the port J performs the functions of the 16-bit timer output
and the external interrupt input.
disabled.
enable input in the PJIE register.
is set to stop driving of pins during STOP mode.
Port J data register
Port J output control register
Port J function register 1
Reserved
Port J pull-up control register
Port J input control register
The port J is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in
Reset initializes all bits of the port J as to perform as the general-purpose ports with input, output and pull-up
To use the external interrupt input for releasing STOP mode, select this function in the PJFR1 register and
These settings enable the interrupt input even if the CGSTBYCR<DRVE> bit in the clock/mode control block
Port J (PJ0 to PJ7)
Note:In modes other than STOP mode, interrupt input is enabled regardless of the PJFR register setting if
Note:Access to the "reserved" areas is prohibited.
Port J Circuit Type
Port J Register
input is enabled in PJIE. Make sure to disable unused interrupts when programming the device.
T7
7
T7
6
Register name
T9
5
Page 144
T9
4
PJDATA
PJPUP
PJFR1
PJCR
PJIE
-
T7
3
T7
Base Address = 0x4000_0240
2
TMPM333FDFG/FYFG/FWFG
Address (Base+)
0x002C
0x0000
0x0004
0x0008
0x0010
0x0038
T7
1
T7
0