TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 333

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.3.3
31-8
7-4
3
2-0
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
(Example: If fc = 40MHz)
Bit
1100 (128 conversion clock)
1101 (512 conversion clock)
1001 (16 conversion clock)
1010 (24 conversion clock)
1011 (32 conversion clock)
0011 (64 conversion clock)
1000 (8 conversion clock)
−
TSH[3:0]
−
ADCLK[2:0]
A clock count required for conversion is 46 clocks at the minimum.
Examples of sample hold time and conversion time as shown as below.
<TSH[3:0]>
Bit Symbol
ADCLK (Conversion Clock Setting Register)
Note:Do not change the setting of the AD conversion clock during AD conversion.
31
23
15
0
0
0
7
1
-
-
-
R
R/W
R
R/W
Type
30
22
14
Sample hold
0
0
0
6
0
Read as 0.
Select the AD sample hold time.
1000: 8 conversion clock
1001: 16 conversion clock
1010: 24 conversion clock
1011: 32 conversion clock
0011: 64 conversion clock
1100: 128 conversion clock
1101: 512 conversion clock
The setup other than those above: Reserved
Read as 0.
Select the AD conversion clock.
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
111: Reserved
-
-
-
12.8 μs
0.2 μs
0.4 μs
0.6 μs
0.8 μs
1.6 μs
3.2 μs
time
TSH
29
21
13
0
0
0
5
0
-
-
-
13.75 μs
000 (fc)
1.15 μs
1.35 μs
1.55 μs
1.75 μs
2.55 μs
4.15 μs
Page 313
28
20
12
0
0
0
4
0
-
-
-
001 (fc/2)
27.5μs
2.3 μs
2.7μs
3.1μs
3.5μs
5.1μs
8.3μs
Conversion time(<ADCLK[2:0]> setting)
27
19
11
Function
0
0
0
3
0
-
-
-
-
010 (fc/4)
10.2μs
16.6μs
55.0μs
4.6 μs
5.4μs
6.2μs
7.0μs
26
18
10
0
0
0
2
0
-
-
-
TMPM333FDFG/FYFG/FWFG
011 (fc/8)
110.0μs
10.8μs
12.4μs
14.0μs
20.4μs
33.2μs
9.2μs
ADCLK
25
17
0
0
9
0
1
0
-
-
-
100 (fc/16)
220.0μs
18.4μs
21.6μs
24.8μs
28.0μs
40.8μs
66.4μs
24
16
0
0
8
0
0
0
-
-
-