TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 236

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.4
Registers Description
10.4.4
31-8
7
6
5
4
3
2
1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
RB8
EVEN
PE
OERR
PERR
FERR
SCLKS
IOC
Bit Symbol
SCxCR (Control Register)
Note:Any error flag (OERR, PERR, FERR) is cleared to "0" when read.
RB8
31
23
15
0
0
0
7
0
-
-
-
R
R
R/W
R/W
R
R
R
R/W
R/W
Type
EVEN
30
22
14
0
0
0
6
0
-
-
-
Read as 0.
Receive data bit 8 (For UART)
9th bit of the received data in the 9 bits UART mode.
Parity (For UART)
0: Odd
1: Even
Selects even or odd parity.
"0" : odd parity, "1" : even parity.
The parity bit may be used only in the 7- or 8-bit UART mode.
Add parity (For UART)
0: Disabled
1: Enabled
Controls enabling/ disabling parity.
The parity bit may be used only in the 7- or 8-bit UART mode.
Overrun error flag (Note)
0: Normal operation
1: Error
Parity / Underrun error flag (Note)
0: Normal operation
1: Error
Framing error flag (Note)
0: Normal operation
1: Error
Selecting input clock edge (For I/O Interface)
0: Rising edges
1: Falling edges
Selects input clock edge for data transmission and reception.
Set to "0" in the clock output mode.
Selecting clock (For I/O Interface)
0: Baud rate generator
1: SCLK pin input
PE
29
21
13
0
0
0
5
0
-
-
-
Page 216
OERR
28
20
12
0
0
0
4
0
-
-
-
PERR
27
19
11
Function
0
0
0
3
0
-
-
-
FERR
26
18
10
0
0
0
2
0
-
-
-
TMPM333FDFG/FYFG/FWFG
SCLKS
25
17
0
0
9
0
1
0
-
-
-
IOC
24
16
0
0
8
0
0
0
-
-
-