TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 306

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.6
Data Transfer Procedure in the I2C Bus ModeI2C
11.6
11.6.1
11.6.2
11.6.2.1
SBIxCR1
SBIxI2CAR
SBIxCR2
Data Transfer Procedure in the I2C Bus ModeI2C
<ALS>. (<ALS> must be cleared to "0" when using the addressing format).
first. Then write "0" to SBIxCR2<MST, TRX, BB>, "1" to <PIN>, "10" to <SBIM[1:0]> and "0" to the bit 1 and
0.
First, program SBIxCR1<ACK, SCK[2:0]>. Writing "000" to SBIxCR1<BC[2:0]> at the time.
Next, program SBIxI2CAR by specifying a slave address at <SA[6:0]> and an address recognition mode at
To configure the Serial Bus Interface as a slave receiver, ensure that the serial bus interface pin is at "High"
Device Initialization
Generating the Start Condition and a Slave Address
edgment mode. Write to SBIxDBR a slave address and a direction bit to be transmitted.
the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The SBI outputs the
slave address and the direction bit specified at SBIxDBR with the first eight clocks, and releases the SDA
line in the ninth clock to receive an acknowledgment signal from the slave device.
In the master mode, the SBI holds the SCL line at the "Low" level while <PIN> is = "0".<TRX> changes its
value according to the transmitted direction bit at generation of the INTSBIx interrupt request, provided that
an acknowledgment signal has been returned from the slave device.
Note:Initialization of the serial bus interface circuit must be completed within a period that any device does not
Note:X; Don’t care
In the master mode, the following steps are required to generate the start condition and a slave address.
First, ensure that the bus is free (<BB> = "0"). Then, write "1" to SBIxCR1<ACK> to select the acknowl-
When <BB> = "0", writing "1111" to SBIxCR2<MST, TRX, BB, PIN> generates the start condition on
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to "0".
Note:To output salve address, check with software that the bus is free before writing to SBIxDBR. If this rule
Master mode
←
←
←
generate start condition after all devices connected to the bus were initialized. If this rule is not followed,
data may not be received correctly because other devices may start transfer before the initialization of
the serial bus interface circuit is completed.
is not followed, data being output on the bus may get ruined.
7
0
X
0
6
0
X
0
5
0
X
0
4
X
X
1
3
0
X
1
2
X
X
0
1
X
X
0
0
X
X
0
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Specifies ACK and SCL clock.
Specifies a slave address and an address recognition mode.
Configures the SBI as a slave receiver.
TMPM333FDFG/FYFG/FWFG