TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 305

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.5.11
11.5.12
11.5.13
11.5.14
11.5.15
11.5.16
SBIxSR<AAS> is set to "1" on receiving the general-call address or the slave address that matches the value
specified at SBIxI2CAR.
when data is written to or read from SBIxDBR.
i.e., the eight bits following the start condition are all zeros.
request causes ACK signal to be read.
condition.
bus interface circuit. After a reset, all control registers and status flags are initialized to their reset values. When
the serial bus interface is initialized, <SWRST> is automatically cleared to "0".
When the SBI operates as a slave device in the address recognition mode (SBIxI2CAR<ALS>="0"),
When <ALS> is "1", <AAS> is set to "1" when the first data word has been received. <AAS> is cleared to "0"
When the SBI operates as a slave device, SBIxSR<AD0> is set to "1" when it receives the general-call address;
<AD0> is cleared to "0" when the start or stop condition is detected on the bus.
SBIxSR<LRB> is set to the SDA line value that was read at the rising of the SCL line.
In the acknowledgment mode, reading SBIxSR<LRB> immediately after generation of the INTSBIx interrupt
Reading or writing SBIxDBR initiates reading received data or writing transmitted data.
When the SBI is acting as a master, setting a slave address and a direction bit to this register generates the start
The SBIxBR0<I2SBI> register determines if the SBI operates or not when it enters the IDLE mode.
This register must be programmed before executing an instruction to switch to the standby mode.
If the serial bus interface circuit locks up due to external noise, it can be initialized by using a software reset.
Writing "10" followed by "01" to SBIxCR2<SWRST[1:0]> generates a reset signal that initializes the serial
Note:A software reset causes the SBI operating mode to switch from the I2C mode to the port mode.
Slave Address Match Detection Monitor
General-call Detection Monitor
Last Received Bit Monitor
Data Buffer Register (SBIxDBR)
Baud Rate Register (SBIxBR0)
Software Reset
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TMPM333FDFG/FYFG/FWFG