TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 91

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.5.2.4
7.5.2.5
7.5.2.6
enter the ISR.
is recommended at the service routine programming and how the source is cleared.
(1)
(2)
The CPU detects an interrupt request with the highest priority.
On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack then
An ISR requires specific programming according to the application to be used. This section describes what
Detection by CPU
CPU processing
Interrupt Service Routine (ISR)
M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No extra
programming is required for them.
is being executed. We recommend you to push the contents of general-purpose registers that might be
rewritten.
the CG Interrupt Request Clear (CGICRCG) Register.
at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source automatically
clears the interrupt request signal from the clock generator.
in the CGICRCG register. When an active edge occurs again, a new interrupt request will be detected.
An ISR normally pushes register contents to the stack and handles an interrupt as required. The Cortex-
Push the contents of other registers if needed.
Interrupt requests with higher priority and exceptions such as NMI are accepted even when an ISR
If an interrupt source is used for clearing a standby mode, each interrupt request must be cleared with
If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared
If an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value
Pushing during ISR
Clearing an interrupt source
Page 71
TMPM333FDFG/FYFG/FWFG