TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 266

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.12
Transmission
10.12
10.12.1
10.12.2
10.12.3
10.12.2.1
10.12.2.2
10.12.3.1
In UART mode, it generates a transmit clock (TXDCLK) on every 16th clock pulse.
Transmission
The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of the receive counter.
SIOCLK
TXDCLK
to the TXD pin on the falling edge of the shift clock outputted from the SCLK pin.
to the TXD pin on the rising or falling edge of the SCLK input signal according to the SCxCR<SCLKS>
setting.
the next TXDCLK and the transmit shift clock signal is also generated.
INTTXx is generated upon completion of data transmission.
buffer is moved to the transmit shift register. The INTTXx interrupt is generated at the same time and the
transmit buffer empty flag (SCxMOD2<TBEMP>) is set to "1". This flag indicates that the next transmit data
can be written. When the next data is written to the transmit buffer, the <TBEMP> flag is cleared to "0".
Transmission Counter
Transmission Control
Transmit Operation
In the SCLK output mode with SCxCR<IOC> set to "0", each bit of data in the transmit buffer is outputted
In the SCLK input mode with SCxCR<IOC> set to "1", each bit of data in the transmit buffer is outputted
When the transmit data is written in the transmit buffer, data transmission is initiated on the rising edge of
If double buffering is disabled, the CPU writes data only to Transmit shift Buffer and the transmit interrupt
If double buffering is enabled (including the case the transmit FIFO is enabled), data written to the transmit
I/O Interface Mode
UART Mode
Operation of Transmission Buffer
15 16
Figure 10-6 Generation of Transmission Clock
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TMPM333FDFG/FYFG/FWFG
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