TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 364

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.3
Operations
13.3
13.3.1
13.3.2
Operations
Detecting time can be selected between 2
time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer out pin
(WDTOUT) output "Low".
the watchdog timer should be cleared by software instruction before INTWDT interrupt generates. If the binary
counter is not cleared, the non-maskable interrupt generates by INTWDT. Thus CPU detects malfunction (run-
way), malfunction countermeasure program is performed to return to the normal operation.
watchdog timer out pin to reset pins of peripheral devices.
frequency clock is stopped. Before transition to these modes, the watchdog timer should be disabled.
The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input.
To detect malfunctions (runaways) of the CPU caused by noise or other disturbances, the binary counter of
Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting the
The watchdog timer begins operation immediately after a reset is cleared.
If not using the watchdog timer, it should be disabled.
The watchdog timer cannot be used in the STOP mode, SLEEP mode and SLOW mode where high-speed
In IDLE mode, its operation depends on the WDMOD <I2WDT> setting.
Also, the binary counter is automatically stopped during debug mode.
Basic Operation
Operation Mode and Status
Note:This product does not include a watchdog timer out pin (WDTOUT).
15
, 2
17
Page 344
, 2
19
, 2
21
, 2
23
and 2
25
by the WDMOD<WDTP[2:0]>. The detecting
TMPM333FDFG/FYFG/FWFG