TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 240

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.4
Registers Description
2
1-0
Bit
WBUF
SWRST[1:0]
Note 1: While data transmission is in progress, any software reset operation must be executed twice in succession.
Note 2: A software reset requires 2 clocks-duration at the time between the end of recognition and the start of exe-
Bit Symbol
cution of software reset instruction.
R/W
R/W
Type
Double-buffer
0: Disabled
1 : Enabled
This parameter enables or disables the transmit/receive double buffers to transmit (in both SCLK output/input
modes) and receive (in SCLK output mode) data in the I/O interface mode and to transmit data in the UART
mode.
When receiving data in the I/O interface mode (SCLK input) and UART mode, double buffering is enabled in
both cases that 0 or 1 is set to <WBUF> bit.
Software reset
Overwriting "01" in place of "10" generates a software reset. When this software reset is executed, the following
bits are initialized and the transmit/receive circuit, the transmit circuit and the FIFO become initial state (see
Note1 and Note2).
SCxMOD0
SCxMOD1
SCxMOD2
Register
SCxCR
Page 220
TBEMP, RBFLL, TXRUN
OERR, PERR, FERR
RXE
TXE
Bit
Function
TMPM333FDFG/FYFG/FWFG