TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 268

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.12
Transmission
Transmit FIFO fourth stage
Transmit interrupt(INTTXx)
10.12.3.3
10.12.3.4
Transmit shift register
SCxMOD2<TBEMP>
SCxMOD1<TXE>
Transmit buffer
transmission is completed and underrun error will not occur.
before the next frame clock input, which occurs upon completion of data transmission from transmit shift
register, an under-run error occurs and SCxCR<PERR> is set to "1".
Second stage
(1)
(2)
(3)
If SCLK is set to generate clock the I/O interface mode, the SCLK output automatically stops when all data
The timing of suspension and resume of SCLK output is different depending on the buffer and FIFO usage.
If the transmit FIFO is disabled in the I/O interface SCLK input mode and if no data is set in transmit buffer
Third stage
First stage
I/O interface Mode/Transmission by SCLK Output
Under-run error
the other side of communication can be enabled. The SCLK output resumes when the next data is written
in the buffer.
transmit buffer. The SCLK output resumes when the next data is written in the buffer.
the SCLK output stops. The next data is written, SCLK output resumes.
stop and the transmission stops.
The SCLK output stops each time one frame of data is transferred. Handshaking for each data with
The SCLK output stops upon completion of data transmission of the transmit shift register and the
The transmission of all data stored in the transmit shift register, transmit buffer and FIFO is completed,
If SCxFCNF<RXTXCNT> is configured, SCxMOD0<TXE> bit is cleared at the same time as SCLK
Single Buffer
Double Buffer
FIFO
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 1
DATA 5
DATA 4
DATA 3
DATA 2
Page 248
DATA 2
DATA 5
DATA 4
DATA 3
DATA 3
DATA 5
DATA 4
DATA 4
TMPM333FDFG/FYFG/FWFG
DATA 5
DATA 5