TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 62

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

6.3
Clock control
6.3.4
6.3.5
the input frequency to oscillator can be low, and the internal clock be made high-speed.
function.
count. After the specified time is reached, the system clock is output and the CPU starts operation.
in consideration of the stability time of the PLL and the internal oscillator.
(instruction). After the completion of warm-up is confirmed, switch the system clock by setting the
CGCKSEL<SYSCK>.
CGCKSEL<SYSCKFLG>
Clock Multiplication Circuit (PLL)
Warm-up function
This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock (fosc.) As a result,
The PLL is disabled after reset. To enable the PLL, set "1" to the CGOSCCR<PLLON> bit.
The PLL requires a certain amount of time to be stabilized, which should be secured using the warm-up
The warm-up function secures the stability time for the oscillator and the PLL with the warm-up timer.
The warm-up function is used when returning from STOP/SLEEP mode.
In this case, an interrupt for returning from the low power consumption mode triggers the automatic timer
In STOP/ SLEEP modes, the PLL is disabled. When returning from these modes, configure the warm-up time
How to configure the warm-up function.
Specify the count up clock for the warm-up counter in the CGOSCCR<WUPSEL> bit.
The warm-up time can be selected by setting the CGOSCCR<WUPT[2:0]>.
The CGOSCCR<WUEON><WUEF> is used to confirm the start and completion of warm-up through software
When clock switching occurs, the current system clock can be checked by monitoring the
Table 6-1 shows the warm-up time.
Table 6-1 Warm-up Time (fosc = 10MHz, fs = 32.768kHz)
CGOSCCR<WUPT[2:0]>
Note:It takes approximately 200μs for the PLL to be stabilized.
Note:The warm-up timer operates according to the oscillation clock, and it may contain errors if there
Warm-up time options
is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be taken as
approximate time.
000
001
010
011
100
101
110
111
2
2
2
2
2
2
2
10
11
12
13
14
15
16
/input frequency
/input frequency
/input frequency
/input frequency
/input frequency
/input frequency
/input frequency
CGOSCCR<WUPSEL> = "0"
−
High-speed clock (fosc)
Page 42
Without WUP
1.638 (ms)
3.277 (ms)
6.554 (ms)
102.4 (μs)
204.8 (μs)
409.6 (μs)
819.2 (μs)
2
2
2
2
2
2
2
15
16
17
18
6
7
8
/input frequency
/input frequency
/input frequency
/input frequency
/input frequency
/input frequency
/input frequency
CGOSCCR<WUPSEL> = "1"
−
Low-speed clock (fs)
TMPM333FDFG/FYFG/FWFG
1.953 (ms)
3.906 (ms)
7.813 (ms)
With WUP
1.0 (s)
2.0 (s)
4.0 (s)
8.0 (s)