TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 412

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15.2
Operation Mode
15.2.10.1
See Table 15-6 for the transfer format of this command.
RAM Transfer Command
1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed de-
2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to
3. The 3rd byte transmitted from the controller to the target board is a command. The code for the
4. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to
scription of how the serial operation mode is determined, see "15.2.10.6 Determination of a Serial
Operation Mode" described later. If it is determined as UART mode, the boot program then checks
if the SIO0 is programmable to the baud rate at which the 1st byte was transferred. During the
first-byte interval, the RXE bit in the SC0MOD register is cleared.
the 1st byte. The boot program echoes back the first byte: 0x86 for UART mode and 0x30 for I/
O Interface mode.
RAM Transfer command is 0x10.
the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive
error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the state
・ To communicate in UART mode
・ To communicate in I/O Interface mode
・ UART mode
・ I/O Interface mode
baud rate. If the serial operation mode is determined as UART, then the boot program checks
if the SIO0 can be programmed to the baud rate at which the first byte was transferred. If
that baud rate is not possible, the boot program aborts, disabling any subsequent communi-
cations.
the desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent
bytes at a rate equal to the desired baud rate.
in monitoring its logic transitions. If the baud rate of the incoming data is high or the chip’s
operating frequency is high, the CPU may not be able to keep up with the speed of logic
transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of
the desired baud rate; then the boot program calculates 16 times that as the desired baud rate.
When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured
for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC
timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode,
the boot program does not check the receive error flag; thus there is no such thing as error
acknowledge (bit 3, 0x08).
boot program programs the SC0BRCR and sends back 0x86 to the controller as an acknowl-
edge. If the SIO0 is not programmable at that baud rate, the boot program simply aborts with
no error indication. Following the 1st byte, the controller should allow for a time-out period
of five seconds. If it does not receive 0x86 within the allowed time-out period, the controller
should give up the communication. The boot program sets the RXE bit in the SC0MOD0
register to enable reception ("1") before loading the SIO transmit buffer with 0x86.
in I/O Interface mode (clocked by the rising edge of SCLK0), writes 0x30 to the SC0BUF.
Then, the SIO0 waits for the SCLK0 signal to come from the controller. Following the
transmission of the 1st byte, the controller should send the SCLK clock to the target board
after a certain idle time (several microseconds). This must be done at 1/16 the desire baud
rate. If the 2nd byte, which is from the target board to the controller, is 0x30, then the
controller should take it as a go-ahead. The controller must then deliver the 3rd byte to the
target board at a rate equal to the desired baud rate. The boot program sets the RXE bit in
the SC0MOD register to enable reception before loading the SIO transmit buffer with 0x30.
Send, from the controller to the target board, 0x86 in UART data format at the desired
Send, from the controller to the target board, 0x30 in I/O Interface data format at 1/16 of
In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port
If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the
The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0
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TMPM333FDFG/FYFG/FWFG