TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 344

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.3
Registers
12.3.12
31-16
15-6
5-2
1
0
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit symbol
After reset
Bit
−
ADR2[9:0]
−
OVR2
ADR2RF
Bit Symbol
Note:Access to this register must be a half word or a word access.
ADREG2A (AD Conversion Result Register 2A)
31
23
15
0
0
0
7
0
-
-
ADR2
R
R
R
R
R
Type
30
22
14
0
0
0
6
0
-
-
Read as 0.
AD conversion result
Conversion result is stored. For information about the correlation between the conversion channel and the
conversion result register, refer to the Table 12-2, chapter 12.4.5.7.
Read as 0.
Overrun flag
0: Not generated.
1: Generated.
If a conversion result is overwritten before reading <ADR2>, "1" is set.
This bit is "0" cleared when it is read.
AD conversion result storage flag
0: Conversion result is not stored.
1: Conversion result is stored.
If a conversion result is stored, "1" is set.
This bit is "0" cleared when the conversion result is read.
29
21
13
0
0
0
5
0
-
-
-
Page 324
28
20
12
0
0
0
4
0
-
-
-
ADR2
27
19
11
Function
0
0
0
3
0
-
-
-
26
18
10
0
0
0
2
0
-
-
-
TMPM333FDFG/FYFG/FWFG
OVR2
25
17
0
0
9
0
1
0
-
-
ADR2RF
24
16
0
0
8
0
0
0
-
-