TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 311

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.6.3.2
INTSBIx interrupt
if TRX = 0
Then go to other processing.
if AL = 0
Then go to other processing.
if AAS = 0
Then go to other processing.
SBIxCR1
SBIxDBR
request is generated, <PIN> is cleared to "0", and the SCL pin is pulled to the "Low" level.
a period of t
carried out.
the slave receiver mode.
In the slave mode, the SBI generates the INTSBIx interrupt request on four occasions:
1) when the SBI has received any slave address from the master.
2) when the SBI has received a general-call address.
3) when the received slave address matches its address.
4) when a data transfer has been completed in response to a general-call.
Also, if the SBI detects Arbitration Lost in the master mode, it switches to the slave mode.
Upon the completion of data word transfer in which Arbitration Lost is detected, the INTSBIx interrupt
When data is written to or read from SBIxDBR or when <PIN> is set to "1", the SCLx pin is released after
In the slave mode, the normal slave mode processing or the processing as a result of Arbitration Lost is
SBIxSR<AL>, <TRX>, <AAS> and <AD0> are tested to determine the processing required.
"Table 11-2 Processing in Slave Mode"shows the slave mode states and required processing.
Example: When the received slave address matches the SBI's own address and the direction bit is "1" in
Note:X; Don’t care
Slave mode (<MST> = "0")
←
←
LOW
X
X
.
X
X
X
X
1
X
0
0
X
X
X
X
Page 291
X
X
Sets the number of bits to be transmitted.
Sets the transmit data.
TMPM333FDFG/FYFG/FWFG