F84045 Asiliant Technologies, F84045 Datasheet - Page 104

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Initializing The Cache: The tag RAM will come up with random data, including the dirty bit. If the cache were
enabled at this point, interesting things would happen. Most of them bad. The cache contains no valid bits. Once the
cache is initialized, it is always valid. The cache is initialized by allowing the normal read-miss process to fill the cache
with valid data. This is done by reading a block of memory which is the size of the cache. Read-hits are disabled to
prevent an uninitialized tag from accidentally indicating a hit, and to force the read cycle to fill the cache with valid
data. Castouts are disabled to prevent invalid data from being cast out into the DRAM during initialization.
The INITCACHE bit, when set overrides the FRZCDIR bit, which it should be set to ‘0’. It also overrides the
WRMODE bit, which may be set either way, and may be set to the desired mode throughout the procedure.
Note: Before setting the INITCACHE bit to ‘1’, Index 21h must be programmed to a value that correctly matches the
physical cache configuration. Failure to do this will result in an invalid initialization of the cache contents and may
also cause a software crash if any software is being executed from cacheable DRAM during the initialization process.
(The reason for the potential software crash is that the 4041 relies on a cache read following each line fill to provide the
read data requested by the CPU, including any code fetches from cacheable DRAM.)
Disabling the Cache: Disabling a write back cache, if not handled carefully, can result in an "Output and pull rug"
instruction if there is dirty data in the cache. To avoid this, a mechanism is provided to dump the dirty data back into
the DRAMs. This involves reading a cacheable memory block twice the size of the cache. Twice the size is required to
make sure each location gets a read-miss, which will cause a cast-out if the dirty bit is set. The cache is then disabled.
No writes should occur during this process.
Switching Between Write Back to Write Through . To switch from write through to write back, nothing special need
be done. Just flip the bit. To switch from write back to write through, the dirty data must be cast out. A block of
cacheable memory twice the size of the cache must be read, with the WRMODE bit set to a 0.
Revision 1.0
Initialize Cache Algorithm.
ENCACHE=0, FRZCDIR=0, INITCACHE=0 to start. WRMODE=X
Set INITCACHE=1.
Read a block of cacheable memory which is at least as large as the cache size.
At the same time, set ENCACHE=1, INITCACHE=0, and WRMODE to desired mode.
Disabling The Cache: Write Through.
(ENCACHE=1, FRZCDIR=0, INITCACHE=0, WRMODE=1 to start (normal write through mode))
Set ENCACHE=0.
Disabling the cache: Write Back.
(ENCACHE=1, FRZCDIR=0, INITCACHE=0, WRMODE=1 to start (normal write back mode))
Read a block of cacheable memory which is at least TWICE as large as the cache size. No cacheable write cycles
Set ENCACHE=0.
Switching from Write Through to Write Back.
(ENCACHE=1, FRZCDIR=0, INITCACHE=0, WRMODE=0 to start (normal write back mode))
Switching from Write Back to Write Through.
(ENCACHE=1, FRZCDIR=0, INITCACHE=0, WRMODE=1 to start (normal write back mode))
Read a block of cacheable memory which is at least TWICE as large as the cache size. No cacheable write cycles
should be done during this time until after the NEXT step.
should be done during this time until after the NEXT step.
2/10/95
Set WRMODE=1.
Set WRMODE=0.
Subject to change without notice
103
Preliminary
Functional Description
CS4041